ics8430ay62l Integrated Device Technology, ics8430ay62l Datasheet - Page 13

• Manufacturer Part Number: ics8430ay62l
• Description: Ics8430-62 500mhz, Crystal-to-3.3v, 2.5v Differential Lvpecl Frequency Synthesizer
• Manufacturer: Integrated Device Technology

ICS8430-62 Datasheet
Recommendations for Unused Input and Output Pins
Inputs:
Crystal Inputs
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied from
XTAL_IN to ground.
REF_CLK Input
For applications not requiring the use of the reference clock, it can be
left floating. Though not required, but for additional protection, a 1kΩ
resistor can be tied from the REF_CLK to ground.
LVCMOS Control Pins
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50Ω
Figure 5A. 3.3V LVPECL Output Termination
ICS8430AY-62 REVISION A JULY 2, 2009
RTT =
((V
3.3V
OH
LVPECL
+ V
OL
) / (V
1
CC
Z
Z
– 2)) – 2
o
o
= 50Ω
= 50Ω
* Z
R1
50Ω
o
RTT
R2
50Ω
V
+
_
CC
3.3V
- 2V
Input
13
Outputs:
TEST Output
The unused TEST output can be left floating. There should be no
trace attached.
LVPECL Outputs
All unused LVPECL outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 5A and 5B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
Figure 5B. 3.3V LVPECL Output Termination
500MHz CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
3.3V
LVPECL
Z
Z
o
o
= 50Ω
= 50Ω
R3
125Ω
R1
84Ω
3.3V
©2009 Integrated Device Technology, Inc.
R4
125Ω
R2
84Ω
+
_
3.3V
Input