ics8430ay62l Integrated Device Technology, ics8430ay62l Datasheet - Page 16

• Manufacturer Part Number: ics8430ay62l
• Description: Ics8430-62 500mhz, Crystal-to-3.3v, 2.5v Differential Lvpecl Frequency Synthesizer
• Manufacturer: Integrated Device Technology

ICS8430-62 Datasheet
The following component footprints are used in this layout example.
All the resistors and capacitors are size 0603.
Power and Grounding
Place the decoupling capacitors C14 and C15, as close as possible
to the power pins. If space allows, placement of the decoupling
capacitor on the component side is preferred. This can reduce
unwanted inductance between the decoupling capacitor and the
power pin caused by the via.
Maximize the pad size of the power (ground) at the decoupling
capacitor. Maximize the number of vias between power (ground) and
the pads. This can reduce the inductance between the power
(ground) plane and the component power (ground) pins.
If V
R7, C11, and C16 in between. Place this RC filter as close to the
V
Clock Traces and Termination
The component placements, locations and orientations should be
arranged to achieve the best clock signal quality. Poor clock signal
quality can degrade the system performance or cause system failure.
In the synchronous high-speed digital system, the clock signal is less
tolerable to poor signal quality than other signals. Any ringing on the
rising or falling edge or excessive ring back can cause system failure.
The trace shape and the trace delay might be restricted by the
available space on the board and the component location. While
routing the traces, the clock signal traces should be routed first and
should be locked prior to routing other signal traces.
Figure 7B. PCB Board Layout for ICS8430-62
ICS8430AY-62 REVISION A JULY 2, 2009
CCA
CCA
PIN 1
pin as possible.
U1
shares the same power supply with V
C14
C1
C15
TL1, TL21N are 50 Ohm
traces and equal length
C11
X1
R7
TL1N
CC,
TL1
insert the RC filter
C16
VCCA
C2
R1
R3
Close to the input
pins of the
receiver
R2
R4
16
GND
VCC
VIA
The matching termination resistors R1, R2, R3 and R4 should be
located as close to the receiver input pins as possible. Other
termination schemes can also be used but are not shown in this
example.
Crystal
The crystal X1 should be located as close as possible to the pins 24
(XTAL_OUT) and 25 (XTAL_IN). The trace length between the X1
and U1 should be kept to a minimum to avoid unwanted parasitic
inductance and capacitance. Other signal traces should not be
routed near the crystal traces.
500MHz CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
• The traces with 50Ω transmission lines TL1 and TL2 at
• Avoid sharp angles on the clock trace. Sharp angle turns
• Keep the clock trace on the same layer. Whenever possible,
• To prevent cross talk, avoid routing other signal traces in
• Make sure no other signal traces are routed between the
FOUT and nFOUT should have equal delay and run adjacent to
each other. Avoid sharp angles on the clock trace.Sharp angle
turns cause the characteristic impedance to change on the
transmission lines.
cause the characteristic impedance to change on the
transmission lines.
avoid any vias on the clock traces. Any via on the trace can
affect the trace characteristic impedance and hence degrade
signal quality.
parallel with the clock traces. If running parallel traces is
unavoidable, allow more space between the clock trace and
the other signal trace.
clock trace pair.
©2009 Integrated Device Technology, Inc.