ics8430ay62l Integrated Device Technology, ics8430ay62l Datasheet - Page 3

• Manufacturer Part Number: ics8430ay62l
• Description: Ics8430-62 500mhz, Crystal-to-3.3v, 2.5v Differential Lvpecl Frequency Synthesizer
• Manufacturer: Integrated Device Technology

ICS8430-62 Datasheet
ICS8430AY-62 REVISION A JULY 2, 2009
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
C
R
R
1, 2, 28, 29,
30, 31, 32
IN
PULLUP
PULLDOWN
Number
11, 12
14, 15
8, 16
3, 4
5, 7
24,
10
13
17
18
19
20
21
22
23
25
26
27
6
9
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
FOUT1, nFOUT1
FOUT0, nFOUT0
M5, M6, M0, M1,
M2, M3, M4
XTAL_OUT
XTAL_SEL
S_CLOCK
VCO_SEL
REF_CLK
nP_LOAD
S_LOAD
XTAL_IN
S_DATA
M7, M8
N0, N2
Name
TEST
V
V
V
V
MR
N1
CCO
CCA
CC
EE
Output
Output
Output
Power
Power
Power
Power
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
Pulldown M divider inputs. Data latched on LOW-to-HIGH transition of nP_LOAD input.
Pulldown Determines output divider value as defined in Table 3C, Function Table.
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown Single-ended reference clock input. LVCMOS/LVTTL interface levels.
Pulldown
Pullup
Pullup
Pullup
Pullup
Test Conditions
Description
LVCMOS/LVTTL interface levels.
LVCMOS/LVTTL interface levels.
Negative supply pins.
Test output which is ACTIVE in the serial mode of operation.
Output driven LOW in parallel mode. LVCMOS/LVTTL interface levels.
Core supply pin.
Differential output pair for the synthesizer. LVPECL interface levels.
Output supply pin for LVPECL outputs.
Differential output pair for the synthesizer. LVPECL interface levels.
Active High Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs FOUTx to go low and the inverted outputs nFOUTx to
go high. When Logic LOW, the internal dividers and the outputs are enabled.
Assertion of MR does not affect loaded M, N, and T values.
LVCMOS/LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register on the
rising edge of S_CLOCK. LVCMOS/LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge of S_CLOCK.
LVCMOS/LVTTL interface levels.
Controls transition of data from shift register into the dividers.
LVCMOS/LVTTL interface levels.
Analog supply pin.
Selects between crystal oscillator or REF_CLK inputs as the PLL reference
source. Selects XTAL inputs when HIGH. Selects REF_CLK when LOW.
LVCMOS/LVTTL interface levels.
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
Parallel load input. Determines when data present at M8:M0 is loaded into M
divider, and when data present at N2:N0 sets the N output divider value.
LVCMOS/LVTTL interface levels.
Determines whether synthesizer is in PLL or bypass mode. When LOW,
synthesizer is in bypass mode, when HIGH,synthesizer is in PLL mode.
LVCMOS/LVTTL interface levels.
3
500MHz CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Minimum
Typical
51
51
4
©2009 Integrated Device Technology, Inc.
Maximum
Units
k
k
pF
Ω
Ω