pi7c8154b Pericom Semiconductor Corporation, pi7c8154b Datasheet - Page 89
pi7c8154b
Manufacturer Part Number
pi7c8154b
Description
Asynchronous 2-port Pci Bridge
Manufacturer
Pericom Semiconductor Corporation
Datasheet
1.PI7C8154B.pdf
(111 pages)
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Part Number:
pi7c8154bNAE
Manufacturer:
PERICOM
Quantity:
20 000
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06-0008
14.1.39
14.1.40
14.1.41
14.1.42
14.1.43
UPSTREAM (S TO P) MEMORY BASE ADDRESS REGISTER – OFFSET
58h
UPSTREAM (S TO P) MEMORY LIMIT ADDRESS REGISTER – OFFSET
58h
UPSTREAM (S TO P) MEMORY BASE ADDRESS UPPER 32-BIT
REGISTER – OFFSET 5Ch
UPSTREAM (S TO P) MEMORY LIMIT ADDRESS UPPER 32-BIT
REGISTER – OFFSET 60h
P_SERR# EVENT DISABLE REGISTER – OFFSET 64h
Bit
3:0
15:4
Bit
19:16
31:20
Bit
31:0
Bit
31:0
Bit
0
Function
64-bit
Addressing
Upstream
Memory Base
Function
64-bit
Addressing
Upstream
Memory Limit
Function
Upstream
Memory Base
Upper 32-bits
Function
Upstream
Memory Base
Upper 32-bits
Function
Reserved
Type
R/O
R/W
Type
R/O
R/W
Type
R/W
Type
R/W
Type
R/O
Page 89 of 111
Description
0000: 32-bit addressing
0001: 64-bit addressing
Reset to 0
Defines the bottom address of an address range used by the bridge to
determine when to forward upstream memory transactions.
Reset to 0
Description
0000: 32-bit addressing
0001: 64-bit addressing
Reset to 0
Defines the top address of an address range used by the bridge to
determine when to forward upstream memory transactions.
Reset to 0
Description
Defines the upper 32-bits of a 64-bit bottom address of an address range
for the bridge to determine when to forward upstream memory read and
write transactions.
Reset to 0
Description
Defines the upper 32-bits of a 64-bit top address of an address range for
the bridge to determine when to forward upstream memory read and write
transactions.
Reset to 0
Description
Returns 0 when read. Reset to 0
MARCH 2006 REVISION 1.12
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
PI7C8154B
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