pi7c8154b Pericom Semiconductor Corporation, pi7c8154b Datasheet - Page 42

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pi7c8154b

Manufacturer Part Number
pi7c8154b
Description
Asynchronous 2-port Pci Bridge
Manufacturer
Pericom Semiconductor Corporation
Datasheet

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06-0008
2.11.4.2
FOR POSTED WRITE TRANSACTIONS:
TARGET DISCONNECT
PI7C8154B returns a target disconnect to an initiator when one of the following conditions is met:
See Section 2.6.4 for a description of write address boundaries, and Section 2.7.3 for a description
of read address boundaries.
The transaction is being entered into the delayed transaction queue.
The read request has already been queued, but read data is not yet available.
Data has been read from target, but it is not yet at head of the read data queue or a posted write
transaction precedes it.
The delayed transaction queue is full, and the transaction cannot be queued.
A delayed read request with the same address and bus command has already been queued.
A locked sequence is being propagated across PI7C8154B, and the read transaction is not a
locked transaction.
PI7C78154B is currently discarding previously pre-fetched read data.
The target bus is locked and the write transaction is a locked transaction.
Use more than 16 clocks to accept this transaction.
The posted write data buffer does not have enough space for address and at least one DWORD
of write data.
A locked sequence is being propagated across PI7C8154B, and the write transaction is not a
locked transaction.
When a target retry is returned to the initiator of a delayed transaction, the initiator must repeat
the transaction with the same address and bus command as well as the data if it is a write
transaction, within the time frame specified by the master timeout value. Otherwise, the
transaction is discarded from the buffers.
PI7C8154B hits an internal address boundary.
PI7C8154B cannot accept any more write data.
PI7C8154B has no more read data to deliver.
Page 42 of 111
MARCH 2006 REVISION 1.12
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
PI7C8154B

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