pi7c8154b Pericom Semiconductor Corporation, pi7c8154b Datasheet - Page 7

• Manufacturer Part Number: pi7c8154b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0008
8
9
10
11
12
13
14
8.1
8.2
8.3
9.1
9.2
9.3
9.4
11.1
11.2
11.3
13.1
13.2
13.3
7.2.3
7.2.4
GENERAL PURPOSE I/O INTERFACE ...............................................................................................67
EEPROM INTERFACE............................................................................................................................69
VITAL PRODUCT DATA (VPD) ............................................................................................................71
CLOCKS.....................................................................................................................................................71
PCI POWER MANAGEMENT................................................................................................................72
RESET.........................................................................................................................................................73
CONFIGURATION REGISTERS ...........................................................................................................75
14.1.1
14.1.2
14.1.3
14.1.4
14.1.5
14.1.6
14.1.7
14.1.8
14.1.9
14.1.10
14.1.11
14.1.12
14.1.13
14.1.14
14.1.15
14.1.16
14.1.17
14.1.18
14.1.19
14.1.20
14.1.21
14.1.22
14.1.23
14.1.24
14.1.25
GPIO CONTROL REGISTERS.........................................................................................................67
SECONDARY CLOCK CONTROL..................................................................................................68
LIVE INSERTION .............................................................................................................................69
AUTO MODE EEPROM ACCESS ...................................................................................................70
EEPROM MODE AT RESET............................................................................................................70
EEPROM DATA STRUCTURE........................................................................................................70
EEPROM CONTENT ........................................................................................................................70
PRIMARY AND SECONDARY CLOCK INPUTS..........................................................................71
SECONDARY CLOCK OUTPUTS ..................................................................................................72
ASYNCHRONOUS MODE...............................................................................................................72
PRIMARY INTERFACE RESET ......................................................................................................73
SECONDARY INTERFACE RESET................................................................................................73
CHIP RESET......................................................................................................................................74
SECONDARY BUS ARBITRATION USING AN EXTERNAL ARBITER .......................................66
BUS PARKING ..............................................................................................................................66
SIGNAL TYPES.........................................................................................................................76
VENDOR ID REGISTER – OFFSET 00h .................................................................................76
DEVICE ID REGISTER – OFFSET 00h ...................................................................................76
COMMAND REGISTER – OFFSET 04h ..................................................................................76
STATUS REGISTER – OFFEST 04h.........................................................................................77
REVISION ID REGISTER – OFFSET 08h................................................................................78
CLASS CODE REGISTER – OFFSET 08h ...............................................................................78
CACHE LINE SIZE REGISTER – OFFSET 0Ch ......................................................................78
PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch.......................................................78
HEADER TYPE REGISTER – OFFSET 0Ch............................................................................79
PRIMARY BUS NUMBER REGISTER – OFFSET 18h ............................................................79
SECONDARY BUS NUMBER REGISTER – OFFSET 18h ......................................................79
SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h ..................................................79
SECONDARY LATENCY TIMER – OFFSET 18h ....................................................................79
I/O BASE REGISTER – OFFSET 1Ch ......................................................................................79
I/O LIMIT REGISTER – OFFSET 1Ch.....................................................................................80
SECONDARY STATUS REGISTER – OFFSET 1Ch ................................................................80
MEMORY BASE REGISTER – OFFSET 20h ...........................................................................81
MEMORY LIMIT REGISTER – OFFSET 20h ..........................................................................81
PREFETCHABLE MEMORY BASE ADDRESS REGISTER – OFFSET 24h ...........................81
PREFETCHABLE MEMORY LIMIT ADDRESS REGISTER – OFFSET 24h ..........................82
PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER – OFFSET 28h82
PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS REGISTER – OFFSET 2Ch
82
I/O BASE ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h .........................................82
I/O LIMIT ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h........................................82
Page 7 of 111
MARCH 2006 REVISION 1.12
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
PI7C8154B