mt45w4mw16p Micron Semiconductor Products, mt45w4mw16p Datasheet - Page 13

• Manufacturer Part Number: mt45w4mw16p
• Description: Async/page Cellularramtm 1.0 Memory
• Manufacturer: Micron Semiconductor Products

Configuration Register Operation
Access Using ZZ#
Figure 9:
Software Access to the Configuration Register
PDF: 09005aef80be1ee8/Source: 09005aef80be1f7f
AsyncCellularRAM_2.fm - Rev. G 10/05 EN
Load Configuration Register Operation
The configuration register (CR) defines how the CellularRAM device performs its trans-
parent self refresh. Altering the refresh parameters can dramatically reduce current con-
sumption during standby mode. Page mode control is also embedded into the CR. This
register can be updated anytime while the device is operating in a standby state.
Figure 12 on page 15 describes the control bits used in the CR. At power up, the CR is set
to 0070h.
The CR can be loaded using a WRITE operation immediately after ZZ# makes a HIGH-
to-LOW transition (Figure 9). The values placed on addresses A[21:0] are latched into the
CR on the rising edge of CE# or WE#, whichever occurs first. LB#/UB# are “Don’t Care.”
Access using ZZ# is WRITE only.
ADDRESS
The contents of the CR can either be read or modified using a software sequence. The
nature of this access mechanism may eliminate the need for ZZ# ball.
If the software mechanism is used, ZZ# can simply be tied to V
cally used for ZZ# control purposes will no longer be required. However, ZZ# should not
be tied to V
software access sequence.
The CR is loaded using a four-step sequence consisting of two READ operations followed
by two WRITE operations (see Figure 10). The read sequence is virtually identical except
that an asynchronous READ is performed during the fourth operation (see Figure 11).
Note that a third READ cycle of the highest address cancels the sequence until a different
address is read.
The address used during all READ and WRITE operations is the highest address of the
CellularRAM device being accessed (3FFFFFh for 64Mb); the content at this address is
changed by using this sequence (note that this is a deviation from the CellularRAM spec-
ification). The data bus is used to transfer data into or out of bits 15–0 of the CR.
Writing to the CR using the software sequence modifies the function of ZZ#. Once the
software sequence loads the CR, the ZZ# level no longer enables PAR operation. PAR
operation will be updated whenever the software sequence loads a new value into the
CR. This ZZ# functionality will continue until the next time the device is powered up.
The operation of ZZ# is not affected if the software sequence is only used to read the
contents of the CR. The use of the software sequence does not affect the ability to per-
form the standard (ZZ#-controlled) method of loading the CR.
WE#
CE#
ZZ#
CC
t < 500ns
Q if the system will use DPD; DPD cannot be enabled or disabled using the
64Mb: 4 Meg x 16 Async/Page CellularRAM 1.0 Memory
ADDRESS VALID
13
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Configuration Register Operation
©2003 Micron Technology, Inc. All rights reserved.
CC
Q. The port line typi-