mt45w4mw16bcgb Micron Semiconductor Products, mt45w4mw16bcgb Datasheet - Page 62

• Manufacturer Part Number: mt45w4mw16bcgb
• Description: 64mb 4 Meg X 16 Async/page/burst Cellularram 1.5 Memory
• Manufacturer: Micron Semiconductor Products

Figure 49:
PDF: 09005aef8247bd51/Source: 09005aef8247bd83
64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN
2nd cycle WRITE
2nd cycle WRITE
2nd cycle WRITE
DQ[15:0] IN
LB#/UB#
A[21:0]
ADV#
WAIT
WE#
OE#
CLK
CE#
Burst WRITE Interrupted by Burst WRITE or READ – Fixed Latency Mode
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
OH
OL
IH
IL
IH
IL
IH
IL
Notes:
High-Z
2nd cycle READ
2nd cycle READ
2nd cycle READ
DQ[15:0] OUT
t CSP
t SP
t SP
t SP
address
1. Nondefault BCR settings for burst WRITE interrupted by burst WRITE or READ in fixed
2. Burst interrupt shown on first allowable clock (such as after first data word written).
3. CE# can stay LOW between burst operations, but CE# must not remain LOW longer than
Valid
LB#/UB#
t HD
t HD
High-Z
latency mode: fixed latency; latency code 2 (3 clocks); WAIT active LOW; WAIT asserted dur-
ing delay.
t
CEM.
t AVH
OE#
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory
V
V
V
V
V
V
IH
IL
IH
IL
OH
OL
t SP
t CLK
t SP
t SP t HD
D0
t CEW
t HD
t SP
t SP
t SP t HD
address
address
Valid
Valid
62
t KHTL
t AVH
WRITE burst interrupted with new WRITE or READ. See Note 2.
t HD
V
V
OH
OL
Micron Technology, Inc., reserves the right to change products or specifications without notice.
High-Z
t CEM (Note 3)
t BOE
t ACLK
t SP
output
Valid
D0
t KOH
t HD
output
Valid
D1
Don’t Care
©2005 Micron Technology, Inc. All rights reserved.
output
D2
Timing Diagrams
Valid
D3
output
Valid
t HD
t HD
t OHZ
Undefined
High-Z