s908ey8ad4cfjer Freescale Semiconductor, Inc, s908ey8ad4cfjer Datasheet - Page 175

• Manufacturer Part Number: s908ey8ad4cfjer
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

15.5.4 Transmission Initiation Latency
When the SPI is configured as a master (SPMSTR = 1), transmissions are started by a software write to
the SPDR ($0012). CPHA has no effect on the delay to the start of the transmission, but it does affect the
initial state of the SCK signal. When CPHA = 0, the SCK signal remains inactive for the first half of the
first SCK cycle. When CPHA = 1, the first SCK cycle begins with an edge on the SCK line from its inactive
to its active level. The SPI clock rate (selected by SPR1–SPR0) affects the delay from the write to SPDR
and the start of the SPI transmission. (See
free-running derivative of the internal MCU clock. It is only enabled when both the SPE and SPMSTR bits
(SPCR) are set to conserve power. SCK edges occur half way through the low time of the internal MCU
clock. Since the SPI clock is free-running, it is uncertain where the write to the SPDR will occur relative
to the slower SCK. This uncertainty causes the variation in the initiation delay shown in
delay will be no longer than a single SPI bit time. That is, the maximum delay between the write to SPDR
and the start of the SPI transmission is two MCU bus cycles for DIV2, eight MCU bus cycles for DIV8, 32
MCU bus cycles for DIV32, and 128 MCU bus cycles for DIV128.
Freescale Semiconductor
CAPTURE STROBE
FOR REFERENCE
FROM MASTER
SCK CPOL = 0
SCK CYCLE #
SCK CPOL =1
FROM SLAVE
SS TO SLAVE
MOSI
MISO
Figure 15-5. Transmission Format (CPHA = 1)
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
MSB
MSB
1
BIT 6
BIT 6
2
Figure
BIT 5
BIT 5
3
15-6.) The internal SPI clock in the master is a
BIT 4
BIT 4
4
BIT 3
BIT 3
5
BIT 2
BIT 2
6
BIT 1
BIT 1
7
Transmission Formats
Figure
LSB
8
LSB
15-6. This
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