s908ey8ad4cfjer Freescale Semiconductor, Inc, s908ey8ad4cfjer Datasheet - Page 142
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s908ey8ad4cfjer
Manufacturer Part Number
s908ey8ad4cfjer
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.S908EY8AD4CFJER.pdf
(278 pages)
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Enhanced Serial Communications Interface (ESCI) Module
13.8.3 ESCI Control Register 3
ESCI control register 3 (SCC3):
R8 — Received Bit 8
T8 — Transmitted Bit 8
ORIE — Receiver Overrun Interrupt Enable Bit
NEIE — Receiver Noise Error Interrupt Enable Bit
FEIE — Receiver Framing Error Interrupt Enable Bit
PEIE — Receiver Parity Error Interrupt Enable Bit
142
•
•
When the ESCI is receiving 9-bit characters, R8 is the read-only ninth bit (bit 8) of the received
character. R8 is received at the same time that the SCDR receives the other 8 bits.
When the ESCI is receiving 8-bit characters, R8 is a copy of the eighth bit (bit 7). Reset has no effect
on the R8 bit.
When the ESCI is transmitting 9-bit characters, T8 is the read/write ninth bit (bit 8) of the transmitted
character. T8 is loaded into the transmit shift register at the same time that the SCDR is loaded into
the transmit shift register. Reset clears the T8 bit.
This read/write bit enables ESCI error CPU interrupt requests generated by the receiver overrun bit,
OR. Reset clears ORIE.
This read/write bit enables ESCI error CPU interrupt requests generated by the noise error bit, NE.
Reset clears NEIE.
This read/write bit enables ESCI error CPU interrupt requests generated by the framing error bit, FE.
Reset clears FEIE.
This read/write bit enables ESCI error CPU interrupt requests generated by the parity error bit, PE.
Reset clears PEIE.
1 = ESCI error CPU interrupt requests from OR bit enabled
0 = ESCI error CPU interrupt requests from OR bit disabled
1 = ESCI error CPU interrupt requests from NE bit enabled
0 = ESCI error CPU interrupt requests from NE bit disabled
1 = ESCI error CPU interrupt requests from FE bit enabled
0 = ESCI error CPU interrupt requests from FE bit disabled
1 = ESCI error CPU interrupt requests from PE bit enabled
0 = ESCI error CPU interrupt requests from PE bit disabled
Stores the ninth ESCI data bit received and the ninth ESCI data bit to be transmitted.
Enables these interrupts:
–
–
–
–
Receiver overrun
Noise error
Framing error
Parity error
Address:
Reset:
Read:
Write:
$0012
Bit 7
R8
U
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
Figure 13-11. ESCI Control Register 3 (SCC3)
= Unimplemented
T8
6
0
R
5
0
R
R
4
0
= Reserved
ORIE
3
0
NEIE
2
0
U = Unaffected
FEIE
1
0
Freescale Semiconductor
PEIE
Bit 0
0
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