s908ey8ad4cfjer Freescale Semiconductor, Inc, s908ey8ad4cfjer Datasheet - Page 147

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s908ey8ad4cfjer

Manufacturer Part Number
s908ey8ad4cfjer
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
SCP1 and SCP0 — ESCI Baud Rate Register Prescaler Bits
SCR2–SCR0 — ESCI Baud Rate Select Bits
ESCI Prescaler Register
The ESCI prescaler register (SCPSC) together with the ESCI baud rate register selects the baud rate for
both the receiver and the transmitter.
Freescale Semiconductor
slave node must be within ±15% of the master node's oscillator. Since a slave node cannot know if it
is running faster or slower than the master node (prior to synchronization), the LINR bit allows the slave
node to differentiate between a 0x00 character of 10.35 bits and a break character of 11.05 bits. The
break symbol length must be verified in software in any case, but the LINR bit serves as a filter,
preventing false detections of break characters that are really 0x00 data characters.
These read/write bits select the baud rate register prescaler divisor as shown in
clears SCP1 and SCP0.
These read/write bits select the ESCI baud rate divisor as shown in
SCR2–SCR0.
Address:
There are two prescalers available to adjust the baud rate. One in the ESCI
baud rate register and one in the ESCI prescaler register.
Reset:
Read:
Write:
$0017
PDS2
Bit 7
0
Figure 13-17. ESCI Prescaler Register (SCPSC)
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
SCR[2:1:0]
SCP[1:0]
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Table 13-7. ESCI Baud Rate Prescaling
0 0
0 1
1 0
1 1
Table 13-8. ESCI Baud Rate Selection
PDS1
6
0
PDS0
5
0
NOTE
PSSB4
4
0
Prescaler Divisor (BPD)
Baud Rate Divisor (BD)
Baud Rate Register
PSSB3
3
0
128
13
16
32
64
1
3
4
1
2
4
8
PSSB2
2
0
Table
PSSB1
13-8. Reset clears
1
0
Table
PSSB0
Bit 0
0
13-7. Reset
I/O Registers
147

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