s908gr16ag4cfj Freescale Semiconductor, Inc, s908gr16ag4cfj Datasheet - Page 171

• Manufacturer Part Number: s908gr16ag4cfj
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

AROVFL— Arbiter Counter Overflow Bit
ARD8— Arbiter Counter MSB
14.9.2 ESCI Arbiter Data Register
ARD7–ARD0 — Arbiter Least Significant Counter Bits
14.9.3 Bit Time Measurement
Two bit time measurement modes, described here, are available according to the state of ACLK.
14.9.4 Arbitration Mode
If AM[1:0] is set to 10, the arbiter module operates in arbitration mode. On every rising edge of SCI_TxD
(output of the ESCI module, internal chip signal), the counter is started. When the counter reaches $38
(ACLK = 0) or $08 (ACLK = 1), RxD is statically sensed. If in this case, RxD is sensed low (for example,
another bus is driving the bus dominant) ALOST is set. As long as ALOST is set, the TxD pin is forced
to 1, resulting in a seized transmission.
If SCI_TxD senses a 0 without having sensed a 0 before on RxD, the counter will be reset, arbitration
operation will be restarted after the next rising edge of SCI_TxD.
Freescale Semiconductor
1. ACLK = 0 — The counter is clocked with one half of the bus clock. The counter is started when a
2. ACLK = 1 — The counter is clocked with one half of the ESCI input clock generated by the ESCI
This read-only bit indicates an arbiter counter overflow. Clear AROVFL by writing any value to
SCIACTL. Writing 0s to AM1 and AM0 resets the counter keeps it in this idle state. Reset clears
AROVFL.
This read-only bit is the MSB of the 9-bit arbiter counter. Clear ARD8 by writing any value to SCIACTL.
Reset clears ARD8.
These read-only bits are the eight LSBs of the 9-bit arbiter counter. Clear ARD7–ARD0 by writing any
value to SCIACTL. Writing 0s to AM1 and AM0 permanently resets the counter and keeps it in this idle
state. Reset clears ARD7–ARD0.
1 = Arbiter counter overflow has occurred
0 = No arbiter counter overflow has occurred
falling edge on the RxD pin is detected. The counter will be stopped on the next falling edge. ARUN
is set while the counter is running, AFIN is set on the second falling edge on RxD (for instance, the
counter is stopped). This mode is used to recover the received baud rate. See
prescaler. The counter is started when a 0 is detected on RxD (see
enabling the bit time measurement with ACLK = 1 leads to immediate start of the counter (see
Figure
measure the length of a received break.
14-23). The counter will be stopped on the next rising edge of RxD. This mode is used to
Address: $000B
Reset:
Read:
Write:
ARD7
Bit 7
Figure 14-20. ESCI Arbiter Data Register (SCIADAT)
0
= Unimplemented
ARD6
6
0
MC68HC908GR16A Data Sheet, Rev. 1.0
ARD5
5
0
ARD4
4
0
ARD3
3
0
ARD2
2
0
Figure
ARD1
1
0
14-22). A 0 on RxD on
Figure
ARD0
Bit 0
0
14-21.
ESCI Arbiter
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