s908gr16ag4cfj Freescale Semiconductor, Inc, s908gr16ag4cfj Datasheet - Page 134

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s908gr16ag4cfj

Manufacturer Part Number
s908gr16ag4cfj
Description
M68hc08 Microcontrollers Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Resets and Interrupts
MODRST — Monitor Mode Entry Module Reset Bit
LVI — Low-Voltage Inhibit Reset Bit
13.3 Interrupts
An interrupt temporarily changes the sequence of program execution to respond to a particular event. An
interrupt does not stop the operation of the instruction being executed, but begins when the current
instruction completes its operation.
13.3.1 Effects
An interrupt:
After every instruction, the CPU checks all pending interrupts if the I bit is not set. If more than one
interrupt is pending when an instruction is done, the highest priority interrupt is serviced first. In the
134
1 = Last reset caused by forced monitor mode entry.
0 = POR or read of SRSR since any reset
1 = Last reset caused by low-power supply voltage
0 = POR or read of SRSR since any reset
Saves the CPU registers on the stack. At the end of the interrupt, the RTI instruction recovers the
CPU registers from the stack so that normal processing can resume.
Sets the interrupt mask (I bit) to prevent additional interrupts. Once an interrupt is latched, no other
interrupt can take precedence, regardless of its priority.
Loads the program counter with a user-defined vector address
STACKING
1. High byte of index register is not stacked.
ORDER
5
4
3
2
1
Figure 13-3. Interrupt Stacking Order
PROGRAM COUNTER (HIGH BYTE)
PROGRAM COUNTER (LOW BYTE)
INDEX REGISTER (LOW BYTE)
MC68HC908GR16A Data Sheet, Rev. 1.0
CONDITION CODE REGISTER
ACCUMULATOR
(1)
$00FF DEFAULT ADDRESS ON RESET
1
2
3
4
5
UNSTACKING
ORDER
Freescale Semiconductor

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