s908qy2ad1vdwer Freescale Semiconductor, Inc, s908qy2ad1vdwer Datasheet - Page 144

• Manufacturer Part Number: s908qy2ad1vdwer
• Description: Mc68hc908qt4a Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

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BCFE — Break Clear Flag Enable Bit
15.2.3 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes. If enabled, the
break module will remain enabled in wait and stop modes. However, since the internal address bus does
not increment in these modes, a break interrupt will never be triggered.
15.3 Monitor Module (MON)
The monitor module allows debugging and programming of the microcontroller unit (MCU) through a
single-wire interface with a host computer. Monitor mode entry can be achieved without use of the higher
test voltage, V
requirements for in-circuit programming.
Features include:
15.3.1 Functional Description
Figure 15-9
The monitor module receives and executes commands from a host computer.
Figure
a host computer via a standard RS-232 interface.
Simple monitor commands can access any memory address. In monitor mode, the MCU can execute
code downloaded into RAM by a host computer while most MCU pins retain normal operating mode
functions. All communication between the host computer and the MCU is through the PTA0 pin. A
level-shifting and multiplexing interface is required between PTA0 and the host computer. PTA0 is used
in a wired-OR configuration and requires a pullup resistor.
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for
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unauthorized users.
This read/write bit enables software to clear status bits by accessing status registers while the MCU is
in a break state. To clear status bits during the break state, the BCFE bit must be set.
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1 = Status bits clearable during break
0 = Status bits not clearable during break
Normal user-mode pin functionality
One pin dedicated to serial communication between MCU and host computer
Standard non-return-to-zero (NRZ) communication with host computer
Standard communication baud rate (7200 @ 2-MHz bus frequency)
Execution of code in random-access memory (RAM) or FLASH
FLASH memory security feature
FLASH memory programming interface
Use of external 9.8304 MHz oscillator to generate internal frequency of 2.4576 MHz
Simple internal oscillator mode of operation (no external clock or high voltage)
Monitor mode entry without high voltage, V
$FF)
Normal monitor mode entry if V
15-11, and
shows a simplified diagram of monitor mode entry.
TST
, as long as vector addresses $FFFE and $FFFF are blank, thus reducing the hardware
Figure 15-12
MC68HC908QYA/QTA Family Data Sheet, Rev. 2
show example circuits used to enter monitor mode and communicate with
TST
(1)
is applied to IRQ
TST
, if reset vector is blank ($FFFE and $FFFF contain
Figure
Freescale Semiconductor
15-10,