s908qy2ad1vdwer Freescale Semiconductor, Inc, s908qy2ad1vdwer Datasheet - Page 132

• Manufacturer Part Number: s908qy2ad1vdwer
• Description: Mc68hc908qt4a Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Timer Interface Module (TIM)
14.7 I/O Signals
The TIM module can share its pins with the general-purpose I/O pins. See
that are shared.
14.7.1 TIM Channel I/O Pins (TCH1:TCH0)
Each channel I/O pin is programmable independently as an input capture pin or an output compare pin.
TCH0
14.7.2 TIM Clock Pin (TCLK)
TCLK is an external clock input that can be the clock source for the counter instead of the prescaled
internal bus clock. Select the TCLK input by writing 1s to the three prescaler select bits, PS[2:0].
TIM Status and Control Register
Module Characteristics table in the Electricals section. The maximum TCLK frequency is the least of
4 MHz or bus frequency ÷ 2.
14.8 Registers
The following registers control and monitor operation of the TIM:
14.8.1 TIM Status and Control Register
The TIM status and control register (TSC) does the following:
TOF — TIM Overflow Flag Bit
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This read/write flag is set when the counter reaches the modulo value programmed in the TIM counter
modulo registers. Clear TOF by reading the TSC register when TOF is set and then writing a 0 to TOF.
can be configured as buffered output compare or buffered PWM pin.
TIM status and control register (TSC)
TIM control registers (TCNTH:TCNTL)
TIM counter modulo registers (TMODH:TMODL)
TIM channel status and control registers (TSC0 and TSC1)
TIM channel registers (TCH0H:TCH0L and TCH1H:TCH1L)
Enables TIM overflow interrupts
Flags TIM overflows
Stops the counter
Resets the counter
Prescales the counter clock
Reset:
Read:
Write:
Bit 7
TOF
0
0
Figure 14-4. TIM Status and Control Register (TSC)
= Unimplemented
TOIE
MC68HC908QYA/QTA Family Data Sheet, Rev. 2
6
0
The minimum TCLK pulse width is specified in the Timer Interface
TSTOP
5
1
TRST
0
4
0
3
0
0
PS2
2
0
Figure 14-1
PS1
1
0
Freescale Semiconductor
Bit 0
PS0
0
for the port pins
14.8.1