ltc4215-1 Linear Technology Corporation, ltc4215-1 Datasheet - Page 8

• Manufacturer Part Number: ltc4215-1
• Description: Hot Swap Controller With Adc And I2c Compatible Monitoring
• Manufacturer: Linear Technology Corporation

PIN FUNCTIONS
LTC4215-1
the GATE pin is high. See Applications Information. The
start-up current limit folds back linearly from 25mV sense
voltage at 0.6V to 10mV at 0.2V on the FB pin. Foldback
is not active once the part leaves start-up and the current
limit is increased to 75mV.
GATE: Gate Drive for External N-channel MOSFET. An inter-
nal 20μA current source charges the gate of the MOSFET.
No compensation capacitor is required on the GATE pin,
but a resistor and capacitor network from this pin to ground
may be used to set the turn-on output voltage slew rate.
During turn-off there is a 1mA pull-down current. During
a short circuit or undervoltage lockout (V
a 450mA pull-down current source between GATE and
SOURCE is activated.
GND: Device Ground.
GPIO1: General Purpose Input/Output and Signals Power
Good/Bad. Open drain logic output that is pulled to ground
if bit B6 is reset. Status register bit C6 indicates if GPIO1
is high or low. High impedance output (high) by default.
GPIO1 may also be confi gured to indicate power-good
or power-bad as detected by the FB pin in status bit C3.
See applications information. Tie to ground if unused.
Confi gure according to Table 2 and 3.
GPIO2: General Purpose Input/Output and Fault Alert
Output. Open drain logic output that is pulled to ground
when bit D6 is set. Status register bit C5 indicates if GPIO2
is high or low. GPIO2 may be confi gured as an output that
is pulled to ground when a fault occurs to alert the host
controller. A fault alert is enabled by the ALERT register.
GPIO2 is confi gured as a general purpose output (high)
with all alerts disabled by default. See Applications In-
formation. Tie to ground if unused. Confi gure according
to Tables 3 and 5.
GPIO3: General Purpose Input/Output. Open drain logic
output that is pulled to ground when bit D7 is set. Status
register bit C2 indicates if GPIO3 is high or low. GPIO3
is confi gured as output low by default. See Applications
Information. Tie to ground if unused. Confi gure accord-
ing to Table 5.
INTV
a 0.1μF capacitor from this pin to ground.
8
CC
: Low Voltage Supply Decoupling Output. Connect
DD
or INTV
CC
),
ON: On Control Input. A rising edge turns on the external
N-channel MOSFET and a falling edge turns it off. This
pin also confi gures the state of the FET On bit in the con-
trol register (and hence the external MOSFET) at power
up. For example, if the ON pin is tied high, then the FET
On bit (A3 in Table 2) goes high 100ms after power-up.
Likewise if the ON pin is tied low then the part remains
off after power-up until the FET On bit is set high using
the I
the fault register.
OV: Overvoltage Comparator Input. Connect this pin to an
external resistive divider from V
pin rises above 1.235V, an overvoltage fault is detected
and the GATE turns off. Tie to GND if unused.
SCL: Serial Bus Clock Input. Data at the SDA pin is shifted
in or out on rising edges of SCL. This is a high impedance
pin that is generally driven by an open-collector output
from a master controller. An external pull-up resistor or
current source is required.
SDAO: Serial Bus Data Output. Open-drain output for send-
ing data back to the master controller or acknowledging a
write operation. Normally tied to SDAI to form the SDA line.
An external pull-up resistor or current source is required.
Internally tied to SDAI in SSOP package.
SDAI: Serial Bus Data Input. A high impedance input for
shifting in address, command or data bits. Normally tied
to SDAO to form the SDA line. Internally tied to SDAO in
SSOP package.
SDA: Serial Bus Data Input/Output Line. Formed by inter-
nally tying the SDAO and SDAI lines together. An external
pull-up resistor or current source is required.
SENSE
to the input of the current sense resistor. Must be con-
nected to the same trace as V
SSOP package.
SENSE
the output of the current sense resistor. The current limit
circuit controls the GATE pin to limit the sense voltage
between the SENSE and V
SOURCE: N-channel MOSFET Source and ADC Input.
Connect this pin to the source of the external N-channel
2
C bus. A high-to-low transition on this pin clears
+
–
: Positive Current Sense Input. Connect this pin
: Negative Current Sense Input. Connect this pin to
DD
pins to 25mV or less.
DD
. Internally tied to V
DD
. If the voltage at this
DD
42151f
in