ltc4215-1 Linear Technology Corporation, ltc4215-1 Datasheet
ltc4215-1
Related parts for ltc4215-1
ltc4215-1 Summary of contents
Page 1
... interface may confi gure the part to latch off or automatically restart after the LTC4215-1 detects a cur- rent limit fault. The controller has additional features to interrupt the host when a fault has occurred, provide three general purpose ...
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... LTC4215-1 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) Supply Voltage (V ) ................................ –0.3V to 24V DD Supply Voltage (INTV ) .......................... –0.3V to 6.5V CC Input Voltages GATE-SOURCE (Note 3) .......................... –0. – SENSE , SENSE ................ V DD SOURCE .................................................... –5V to 24V EN, FB, ON, OV, UV ................................ –0.3V to 12V ADR0, ADR1, TIMER, ADIN, SS ................................ –0.3V to INTV GPIO2, GPIO3, SCL, SDA, SDAI, SDAO –0.3V to 6.5V Output Voltages GATE, GPIO1 .......................................... – ...
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... SOURCE V Rising 1. Rising 3.5V V Rising 1. Rising 1. Falling UV FB Rising FB = 1.8V V Rising GPIO1 V Rising GPIO2 V Rising GPIO3 LTC4215-1 MIN TYP MAX l 2.9 3.1 3.4 l 2.55 2.64 2. 22 ...
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... LTC4215-1 ELECTRICAL CHARACTERISTICS temperature range, otherwise specifi cations are at T SYMBOL PARAMETER Other Pin Functions V GPIO1 Pin Output Low Voltage GPIO1(OL) V GPIO2 Output Low Voltage GPIO2(OL) V GPIO3 Output Low Voltage GPIO3(OL) I GPIO1-3 Pin Input Leakage Current GPIO1-3(OH) I SOURCE Pin Input Current ...
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... LSB step size and the single shot measurement. Typical specifi cations are measured from the 1/4, 1/2 and 3/4 areas of the quantization band. Note 6: Guaranteed by design and not subject to test 25° INTV 4.0 3.5 3.0 2.5 2.5 3.0 3.5 4.0 INTV (V) CC 4215 G02 LTC4215-1 MIN TYP MAX UNITS l 1.3 1.7 1 ±1 μA l 0.2 0 400 1000 kHz l ...
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... LTC4215-1 TYPICAL PERFORMANCE CHARACTERISTICS V vs Temperature TH(UV) 1.240 1.238 1.236 1.234 1.232 1.230 –50 – TEMPERATURE (°C) 4215 G04 Current Limit 0.2 0.4 0.6 0.8 1.0 1.2 V (V) FB 4215 G07 ΔV vs Temperature GATE 6 6 12V DD 5.9 5.8 5 3.3V DD 5.6 5.5 5.4 –50 – ...
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... The power bad condition may result in the GPIO1 pin pulling low or going high impedance depending on the confi guration of control register bits A6 and A7. Also a power bad fault is logged in this condi- tion if the LTC4215-1 has fi nished the start-up cycle and LTC4215 25° 12V unless otherwise noted ...
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... LTC4215-1 PIN FUNCTIONS the GATE pin is high. See Applications Information. The start-up current limit folds back linearly from 25mV sense voltage at 0.6V to 10mV at 0.2V on the FB pin. Foldback is not active once the part leaves start-up and the current limit is increased to 75mV. GATE: Gate Drive for External N-channel MOSFET. An inter- nal 20μ ...
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... OV2 + OV2 TM2 + – – 1.235V A/D CONVERTER SOURCE V – SENSE ADDR LTC4215-1 . Allow an additional 10nF the voltage DD if unused GATE CS – CHARGE PUMP AND + SOURCE GATE DRIVER FET ON GP GPI03 + – 1.6V GP GPI02 + – ...
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... If the fi xed internal CC overvoltage comparator, OV2, detects that V than 15.6V, the part immediately generates an overvoltage fault and turns the GATE off. Included in the LTC4215 8-bit A/D converter. The converter has a 3-input multiplexer to select between the ADIN pin, the SOURCE pin and the V voltage interface is provided to read the A/D registers ...
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... The system queries each LTC4215-1 over 2 the I C periodically and reads status and measurement information. A basic LTC4215-1 application circuit is shown in Figure 1. The following sections cover turn-on, turn-off and various faults that the LTC4215-1 detects and acts upon. External component selection is discussed in detail in the Design Example section. ...
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... LTC4215-1 APPLICATIONS INFORMATION The MOSFET is turned on by charging up the GATE with a 20μA current source. When the GATE voltage reaches the MOSFET threshold voltage, the MOSFET begins to turn on and the SOURCE voltage then follows the GATE voltage as it increases. When the MOSFET is turning on, it ramps inrush current ...
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... If the system shuts down due to a fault, it may be desirable to restart the system simply by removing and reinserting a load card. In cases where the LTC4215-1 and the switch reside on a backplane or midplane and the load resides on a plug-in card, the EN pin detects when the plug-in card is 4215 F03 removed ...
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... D6. When D6 is set, GPIO2 will pull low, and when D6 is reset (default) GPIO2 will be high or pulled low due to an alert. The LTC4215-1 will not respond to the alert response address if the GPIO2 pin is being pulled low due to bit D6 being set. See the Typical Applications section for a schematic detailing the behavior of the GPIO2 pin ...
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... APPLICATIONS INFORMATION by removal of the fault condition, the switch is allowed to turn on again. The LTC4215-1 will set bit D2 and turn off in the event of an overcurrent fault, preventing it from remaining in an overcurrent condition. If confi gured to auto-retry, the LTC4215-1 will continually attempt to re- start after cool-down cycles until it succeeds in starting up without generating an overcurrent fault ...
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... TIMER = 14.0V 13.5V (using V OV(FALLING) = 10.75V 10.6V (using V UV(FALLING) = 11.6V 10.85V (using V PG(FALLING placed on the UV pin to prevent F I SENSE RESISTOR R LOAD GPIO1 SS INTV GND TIMER LTC4215-1 ON ADIN EN GPIO3 SDAO ADR1 I LOAD Figure 5. Recommended Layout OV(TH) UV(TH) FB(TH) R8 4215 F05 42151f ...
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... LTC4215-1s, regardless of their individual address settings. Mass write can be disabled by setting register bit A4 to zero. Address (0001 100) is the SMBus Alert Response Address. If the LTC4215-1 is pulling low on the GPIO2 pin due to an alert, it acknowledges this address by broadcasting its address and releasing the C Bus and SMBus, an GPIO2 pin ...
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... Write Protocol The master begins communication with a START condition followed by the seven bit slave address and the R/W bit set to zero, as shown in Figure 7. The addressed LTC4215-1 acknowledges this and then the master sends a command byte which indicates which internal register the master wishes to write ...
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... The transmission is ended when the master sends a STOP condition. If the master continues sending a second data byte Write Word command, the second data byte is acknowledged by the LTC4215-1 but ignored, as shown in Figure 8. Read Protocol The master begins a read operation with a START con- dition followed by the seven bit slave address and the R/W bit set to zero, as shown in Figure 9 ...
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... LTC4215-1 APPLICATIONS INFORMATION Table 2. CONTROL Register A (00h)—Read/Write BIT NAME OPERATION A7:6 GPIO1 Confi gure FUNCTION Power Good Power Good General Purpose Output (Default) General Purpose Input A5 Test Mode Enable Enables Test Mode to Disable the ADC ADC Disable ADC Enable (Default) A4 Mass Write Enable Allows Mass Write Addressing ...
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... OPERATION F7:0 SOURCE Voltage SOURCE Voltage Data, 8-Bit Data with 60.5mV LSB and 15.44V Full Scale Measurement Table 8. ADIN Register G (06h)—Read/Write BIT NAME G7:0 ADIN Voltage Measurement OPERATION ADIN Voltage Data, 8-Bit Data with 4.82mV LSB and 1.23V Full Scale LTC4215-1 42151f 21 ...
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... ADR0 ADR1 TIMER TIMER 0.1μF 1μF 0.003Ω 34k 10Ω 1.74k + – SENSE SENSE GATE SOURCE DD 2.67k OV SDA LTC4215-1 SCL ADR0 ON INTV TIMER SS GND EN ADR1 CC 0.1μF 68nF Q GPIO2 PIN 4215 TA02 + R7 24. R10 R8 24k 24k 910Ω 2.94k ...
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... UFD Package 24-Lead Plastic QFN (4mm × 5mm) (Reference LTC DWG # 05-08-1696 Rev A) 0.70 ±0.05 3.65 ± 0.05 PACKAGE OUTLINE 3.00 REF 4.10 ± 0.05 5.50 ± 0.05 0.75 ± 0.05 4.00 ± 0.10 (2 SIDES) 0.200 REF 0.00 – 0.05 LTC4215 0.05 TYP 2.00 REF PIN 1 NOTCH 0.115 TYP 23 24 0.40 ± 0. 3.00 REF 3.65 ± 0.10 2.65 ± 0.10 (UFD24) QFN 0506 REV A 0.25 ± ...
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... SSOP-28 www.linear.com ● Si7880DP R5 10Ω 22nF 15k –12V R7 24.3k – SENSE GATE SOURCE GPIO1 2.94k 1% LTC4215-1 GPIO2 –12V GPIO3 ADIN EN GND 4215 TA05 LT 0108 • PRINTED IN USA © LINEAR TECHNOLOGY CORPORATION 2008 OUTPUT C L 1000μF –12V 42151f ...