ltc4268cdkd-1-trpbf Linear Technology Corporation, ltc4268cdkd-1-trpbf Datasheet - Page 37

• Manufacturer Part Number: ltc4268cdkd-1-trpbf
• Description: High Power Pd With Synchronous Noopto Flyback Controller
• Manufacturer: Linear Technology Corporation

APPLICATIONS INFORMATION
the actual secondary output voltage. The enable delay time
should be made long enough to ignore the “irrelevant”
portion of the fl yback waveform at light loads.
Even though the LTC4268-1 has a robust gate drive, the gate
transition time slows with very large MOSFETs. Increase
delay time as required when using such MOSFETs.
The enable delay resistor is set with the following
equation:
Keep R
56k.
Primary Gate Delay Time (PGDLY)
Primary gate delay is the programmable time from the
turn-off of the synchronous MOSFET to the turn-on of
the primary side MOSFET. Correct setting eliminates
overlap between the primary side switch and secondary
side synchronous switch(es) and the subsequent current
R
ENDLY
ENDLY
+
V
IN
( )
Figure 15. Typical Power Bootstrapping
k
R
C
TR
Ω
V
TR
greater than 40k. A good starting point is
ON
THRESHOLD
=
t
ENDLY
LTC4268-1
V
I
V
VCC
VCC
GND
V
PG
CC
0
2 616
.
( )
I
VCC
ns
PG
− 30
V
IN
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•
•
•
spike in the transformer. This spike will cause additional
component stress and a loss in regulator effi ciency.
The primary gate delay resistor is set with the following
equation:
A good starting point is 27k.
Soft Start Function
The LTC4268-1 contains an optional soft-start function that
is enabled by connecting an external capacitor between the
SFST pin and ground. Internal circuitry prevents the control
voltage at the V
pin. There is an initial pull-up circuit to quickly bring the
SFST voltage to approximately 0.8V. From there it charges
to approximately 2.8V with a 20μA current source.
The SFST node is discharged to 0.8V when a fault occurs.
A fault occurs when V
current sense voltage is greater than 200mV or the IC’s
thermal (over temperature) shutdown is tripped. When
SFST discharges, the V
to below the minimum current voltage. Once discharged
and the fault removed, the SFST charges up again. In this
manner, switch currents are reduced and the stresses in
the converter are reduced during fault conditions.
The time it takes to fully charge soft-start is:
Converter Start-Up
The standard topology for the LTC4268-1 utilizes a third
transformer winding on the primary side that provides
both feedback information and local V
LTC4268-1 (see Figure 15). This power “bootstrapping”
improves converter effi ciency but is not inherently self-
starting. Start-up is affected with an external “trickle charge”
resistor and the LTC4268-1’s internal V
lockout circuit. The V
hysteresis to facilitate start-up.
R
t
ss
PGDLY
=
C
SFST
( )
k
20
Ω
μ
• .
CMP
1 4
A
=
t
PGDLY
V
pin from exceeding that on the SFST
CC
=
CC
CMP
is too low (undervoltage lockout),
70
9 01
undervoltage lockout has wide
( )
.
k
ns
node voltage is also pulled low
Ω
•
+ 47
C
SFST
LTC4268-1
( )
μ
CC
F
CC
power for the
undervoltage
37
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