c15bc1 aptina, c15bc1 Datasheet - Page 55

• Manufacturer Part Number: c15bc1
• Description: Mt9d014 1/4-inch 2mp Cmos Digital Image Sensor
• Manufacturer: aptina

Electrical Specifications
EXTCLK
Table 14:
Two-Wire Serial Register Interface
Table 15:
PDF: 0526161444/Source:6112702771
MT0D014_DS - Rev. J 5/10 EN
Definition
Input clock frequency
Input clock period
Input clock amplitude
(AC coupled sine wave)
Input clock duty cycle
Input clock jitter
PLL VCO lock time
Input pad capacitance
Input HIGH leakage current
Input LOW leakage current
Input HIGH voltage
(DC coupled)
Input LOW voltage
(DC coupled)
Definition
Input HIGH voltage
Input LOW voltage
Input leakage current
Output LOW voltage
Output LOW current
Tri-state output leakage current
Input pad capacitance
Load capacitance
Electrical Characteristics (EXTCLK)
Two-Wire Serial Register Interface Electrical Characteristics
Notes:
The electrical characteristics of the EXTCLK input are shown in Table 14. The EXTCLK
input supports an AC-coupled sine-wave input clock or a DC-coupled square-wave
input clock.
The electrical characteristics of the two-wire serial register interface (SCLK, S
shown in Table 15. The SCLK and S
Schmitt trigger input, and suppression of input pulses of less than 50ns.
1. 6750 EXTCLK cycles or 1ms, whichever is smaller.
Condition
External coupling
cap value 50–100pF
V
V
At specified I
IN
IN
= V
= D
DD
GND
IL
Condition
No pull-up resistor;
V
At specified I
At specified V
IN
= V
DD
or D
OL
OL
GND
f
t
Symbol
V
EXTCLK
EXTCLK
t
t
JITTER
LOCK
IN
V
V
I
I
IH
_AC
IL
IH
IL
55
MT9D014: 1/4-Inch 2Mp CMOS Digital Image Sensor
DATA
Symbol
C
V
V
C
LOAD
I
V
I
I
O
OL
IN
OL
IH
IN
IL
z
signals feature fail-safe input protection,
166.7
–0.5
Min
–10
–10
0.5
1.0
45
6
0.7 x V
–0.5
Min
8.9
–
–
–
–
–
DD
Aptina reserves the right to change products or specifications without notice.
62.5
Typ
1.0
2.5
16
50
–
–
–
–
Typ
–
–
–
–
–
–
–
–
©2007 Aptina Imaging Corporation. All rights reserved.
Electrical Specifications
0.3 x V
6750
Max
V
0.3 x V
300
1.2
2.9
27
37
55
10
10
DD
Max
18.5
0.4
10
15
1
6
1
DD
+ 0.5
DD
DATA
Preliminary
EXTCLK
cycles
MHz
Unit
V
?A
?A
ns
ps
pF
) are
%
V
V
PP
Unit
mA
?A
?A
pF
pF
V
V
V