c15bc1 aptina, c15bc1 Datasheet - Page 23

• Manufacturer Part Number: c15bc1
• Description: Mt9d014 1/4-inch 2mp Cmos Digital Image Sensor
• Manufacturer: aptina

Figure 10:
PDF: 0526161444/Source:6112702771
MT0D014_DS - Rev. J 5/10 EN
Effect of Limiter on the SMIA Data Path
output image. To understand the reason for this, consider the situation where the sensor
is operating at full resolution and the scaler is enabled with a scaling factor of 32 (half the
number of pixels in each direction). This situation is shown in Figure 10.
Core output: full resolution, x_output_size = x_addr_end - x_addr_start + 1
Scaler output: scaled to half size
Limiter output: scaled to half size, x_output_size = x_addr_end - x_addr_start + 1
In Figure 10, three different stages in the SMIA data path (see “Digital Data Path” on
page 50) are shown. The first stage is the output of the sensor core. The core is running at
full resolution and x_output_size is set to match the active array size. The LINE_VALID
(LV) signal is asserted once per row and remains asserted for N pixel times. The
PIXEL_VALID signal toggles with the same timing as LV, indicating that all pixels in the
row are valid.
The second stage is the output of the scaler, when the scaler is set to reduce the image
size by one-half in each dimension. The effect of the scaler is to combine groups of
pixels. Therefore, the row time remains the same, but only half the pixels out of the
scaler are valid. This is signalled by transitions in PIXEL_VALID. Overall, PIXEL_VALID is
asserted for (N/2) pixel times per row.
The third stage is the output of the limiter when the x_output_size is still set to match the
active array size. Because the scaler has reduced the amount of valid pixel data without
reducing the row time, the limiter attempts to pad the row with (N/2) additional pixels. If
this has the effect of extending LV across the whole of the horizontal blanking time, the
MT9D014 will cease to generate output frames.
A correct configuration is shown in Figure 11 on page 24, in addition to showing the
x_output_size reduced to match the output size of the scaler. In this configuration, the
output of the limiter does not extend LV.
Figure 11 on page 24 also shows the effect of the output FIFO, which forms the final stage
in the SMIA data path. The output FIFO merges the intermittent pixel data back into a
contiguous stream. Although not shown in this example, the output FIFO is also capable
of operating with an output clock that is at a different frequency from its input clock.
LINE_VALID
PIXEL_VALID
LINE_VALID
PIXEL_VALID
LINE_VALID
PIXEL_VALID
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MT9D014: 1/4-Inch 2Mp CMOS Digital Image Sensor
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Programming Restrictions
©2007 Aptina Imaging Corporation. All rights reserved.
Preliminary