c15bc1 aptina, c15bc1 Datasheet - Page 26

• Manufacturer Part Number: c15bc1
• Description: Mt9d014 1/4-inch 2mp Cmos Digital Image Sensor
• Manufacturer: aptina

Control of the Signal Interface
Serial Register Interface
Default Power-Up State
PDF: 0526161444/Source:6112702771
MT0D014_DS - Rev. J 5/10 EN
This section describes the operation of the signal interface in all functional modes.
The serial register interface uses the following signals:
• SCLK
• S
• S
SCLK is an input-only signal and must always be driven to a valid logic level for correct
operation; if the driving device can place this signal in High-Z state, an external pull-up
resistor should be connected on this signal.
S
signal.
S
an alternate slave address. These slave addresses can also be programmed through
R0x31FC.
This interface is described in detail in “EXTCLK” on page 55.
The MT9D014 provides interfaces for pixel data through the CCP2 high-speed serial
interface described by the SMIA specification.
At power up and after a hard or soft reset, the reset state of the MT9D014 is to enable the
SMIA CCP2 high-speed serial interface.
SMIA CCP2 requirements and supports both data/clock signalling and data/strobe
signalling.
The DATA_P, DATA_N, CLK_P, and CLK_N pads are turned off if the SMIA serial disable
bit is asserted (R0x301A–B[12] = 1) or when the sensor is in the soft standby state.
In data/clock mode, the clock remains HIGH when no data is being transmitted. In data/
strobe mode before frame start, clock is LOW and data is HIGH.
DATA
ADDR
DATA
ADDR
is a bidirectional signal. An external pull-up resistor should be connected on this
is a signal which can be optionally enabled and controlled by a GPI pad to select
(through a GPI pad)
26
MT9D014: 1/4-Inch 2Mp CMOS Digital Image Sensor
Aptina reserves the right to change products or specifications without notice.
Control of the Signal Interface
©2007 Aptina Imaging Corporation. All rights reserved.
Preliminary