c15bc1 aptina, c15bc1 Datasheet - Page 29

• Manufacturer Part Number: c15bc1
• Description: Mt9d014 1/4-inch 2mp Cmos Digital Image Sensor
• Manufacturer: aptina

Table 7:
Power-On Reset Sequence
Soft Reset Sequence
PDF: 0526161444/Source:6112702771
MT0D014_DS - Rev. J 5/10 EN
Internal initialization
Wait for frame end
Hardware standby
Software standby
Powered off
POR active
Streaming
PLL lock
State
PLL in System States
Notes:
1. The negation of the RESET_BAR input.
2. A timeout of the internal power-on reset circuit.
When power is applied to the MT9D014, it enters a low-power hardware standby state.
Exit from this state is controlled by the later of two events:
It is possible to hold RESET_BAR permanently negated and rely upon the internal
power-on reset circuit.
When RESET_BAR is asserted, it asynchronously resets the sensor, truncating any frame
that is in progress.
When the sensor leaves the hardware standby state, it waits for power-on reset and
performs an internal initialization sequence that takes 700 EXTCLK cycles. After this
time, it enters a low-power soft standby state. While the initialization sequence is in
progress, the MT9D014 will not respond to READ transactions on its two-wire serial
interface. Therefore, a method to determine when the initialization sequence has
completed is to poll a sensor register; for example, R0x0000. While the initialization
sequence is in progress, the sensor will not respond to its device address and READs
from the sensor will result in a NACK on the two-wire serial interface bus. When the
sequence has completed, READs will return the operational value for the register
(0x1501 if R0x0000 is read).
When the sensor leaves soft standby mode and enables the VCO, an internal delay will
keep the PLL disconnected for up to 6750 EXTCLKs so that the PLL can lock.
The MT9D014 can be reset under software control by writing “1” to software_reset
(R0x0103). A software reset asynchronously resets the sensor, truncating any frame that
is in progress. The sensor starts the internal initialization sequence, while the PLL and
analog blocks are turned off. At this point, the behavior is exactly the same as for the
power-on reset sequence.
1. VCO = voltage-controlled oscillator.
EXTCLKs
6750
700
29
MT9D014: 1/4-Inch 2Mp CMOS Digital Image Sensor
VCO powering up and locking, PLL output bypassed
VCO running, PLL output active
Aptina reserves the right to change products or specifications without notice.
VCO powered down
Control of the Signal Interface
PLL
©2007 Aptina Imaging Corporation. All rights reserved.
Preliminary