mcf54455 Freescale Semiconductor, Inc, mcf54455 Datasheet - Page 31

• Manufacturer Part Number: mcf54455
• Description: 32-bit Microprocessor With Usb On-the-go, Ethernet, Pci, Ddr2/ddr Controller And Encryption
• Manufacturer: Freescale Semiconductor, Inc

5.11
This section provides the AC timings for the SSI in master (clocks driven) and slave modes (clocks input). All timings are given
for non-inverted serial clock polarity (SSI_TCR[TSCKP] = 0, SSI_RCR[RSCKP] = 0) and a non-inverted frame sync
(SSI_TCR[TFSI] = 0, SSI_RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timings
remain valid by inverting the clock signal (SSI_BCLK) and/or the frame sync (SSI_FS) shown in the figures below.
Freescale Semiconductor
1
2
3
Num
S10
All timings specified with a capactive load of 25pF.
SSI_MCLK can be generated from SSI_CLKIN or a divided version of the internal system clock (f
SSI_BCLK can be derived from SSI_CLKIN or a divided version of the internal system clock (f
S1
S2
S3
S4
S5
S6
S7
S8
S9
SSI Timing Specifications
SSI_MCLK cycle time
SSI_MCLK pulse width high / low
SSI_BCLK cycle time
SSI_BCLK pulse width
SSI_BCLK to SSI_FS output valid
SSI_BCLK to SSI_FS output invalid
SSI_BCLK to SSI_TXD valid
SSI_BCLK to SSI_TXD invalid / high impedence
SSI_RXD / SSI_FS input setup before SSI_BCLK
SSI_RXD / SSI_FS input hold after SSI_BCLK
ULPI_DIR / ULPI_NXT
ULPI_DATA[7:0]
(Control Output)
ULPI_DATA[7:0]
(Control Input)
(Data Output)
USB_CLKIN
(Data Input)
ULPI_STP
MCF5445x ColdFire
Description
Table 16. SSI Timing — Master Modes
Figure 15. ULPI Timing Diagram
U2
U2
®
Microprocessor Data Sheet, Rev. 0
U3
U3
U4
U4
Symbol
t
t
MCLK
BCLK
U1
2 × t
8 × t
45%
45%
Min
10
—
—
1
-2
0
0
SYS
SYS
U5
U5
55%
55%
Max
15
15
—
—
—
—
—
—
Electrical Characteristics
sys
).
sys
Units
t
t
MCLK
BCLK
ns
ns
ns
ns
ns
ns
ns
ns
).
Notes
2
3
31