mcf54455 Freescale Semiconductor, Inc, mcf54455 Datasheet - Page 26

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mcf54455

Manufacturer Part Number
mcf54455
Description
32-bit Microprocessor With Usb On-the-go, Ethernet, Pci, Ddr2/ddr Controller And Encryption
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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1
2
3
4
5
6
7
8
DD10 Input Data Hold Relative to DQS.
Num
DD7
DD8
DD9
Electrical Characteristics
26
The SDRAM interface operates at the same frequency as the internal system bus.
Pulse width high plus pulse width low cannot exceed min and max clock period.
Command output valid should be 1/2 the memory bus clock (t
voltage variations.
This specification relates to the required input setup time of DDR memories. The microprocessor’s output setup should be larger
than the input setup of the DDR memories. If it is not larger, then the input setup on the memory is in violation.
SD_D[31:24] is relative to SD_DQS[3]; SD_D[23:16] is relative to SD_DQS[2]
The first data beat is valid before the first rising edge of DQS and after the DQS write preamble. The remaining data beats are valid
for each subsequent DQS edge.
This specification relates to the required hold time of DDR memories.
SD_D[31:24] is relative to SD_DQS[3]; SD_D[23:16] is relative to SD_DQS[2]
Data input skew is derived from each DQS clock edge. It begins with a DQS transition and ends when the last data line becomes
Data input hold is derived from each DQS clock edge. It begins with a DQS transition and ends when the first data line becomes
invalid.
valid. This input skew must include DDR memory output skew and system level board skew (due to routing or other factors).
Data and Data Mask Output Setup (DQ-->DQS)
Relative to DQS (DDR Write Mode)
Data and Data Mask Output Hold (DQS-->DQ)
Relative to DQS (DDR Write Mode)
Input Data Skew Relative to DQS (Input Setup)
Characteristic
Table 13. SDRAM Timing Specifications (continued)
MCF5445x ColdFire
®
Microprocessor Data Sheet, Rev. 0
SDCK
Symbol
t
t
t
t
QS
QH
IS
IH
) plus some minor adjustments for process, temperature, and
(0.25 x t
+ 0.5ns
Min
1.0
1.0
SDCK
)
Max
1.0
Freescale Semiconductor
Unit
ns
ns
ns
ns
Notes
4
5
6
7
8

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