mcf5274l Freescale Semiconductor, Inc, mcf5274l Datasheet - Page 52

• Manufacturer Part Number: mcf5274l
• Description: Mcf5275 Integrated Microprocessor Family Hardware
• Manufacturer: Freescale Semiconductor, Inc

Preliminary Electrical Characteristics
10.6 External Interface Timing Characteristics
Table 48
52
NOTES:
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Frequency un-LOCK Range
Frequency LOCK Range
CLKOUT Period Jitter,
Frequency Modulation Range Limit
(f
ICO Frequency. f
sys/2
Peak-to-peak Jitter (Clock edge to clock edge)
Long Term Jitter (Averaged over 2 ms interval)
All values given are initial design targets and subject to change.
All internal registers retain data at 0 Hz.
“Loss of Reference Frequency” is the reference frequency detected internally, which transitions the PLL into self
clocked mode.
Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls below
f
This parameter is guaranteed by characterization before qualification rather than 100% tested.
Proper PC board layout procedures must be followed to achieve specifications.
Load Capacitance determined from crystal manufacturer specifications and will include circuit board parasitics.
This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits
in the synthesizer control register (SYNCR).
Assuming a reference is available at power up, lock time is measured from the time V
RSTOUT negating. If the crystal oscillator is being used as the reference for the PLL, then the crystal start up time
must be added to the PLL lock time to determine the total start-up time.
PLL is operating in 1:1 PLL mode.
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum
f
signal. Noise injected into the PLL circuitry via V
increase the jitter percentage for a given interval.
Based on slow system clock of 33MHz maximum frequency.
Modulation percentage applies over an interval of 10Ps, or equivalently the modulation rate is 100KHz.
Modulation rate selected must not result in f
range determined by hardware design.
f
LOR
t
sys/2
sys/2
lpll
Max must not be exceeded)
lists processor bus input timings.
= (64
. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock
with default MFD/RFD settings.
= f
ico
*
/ (2
All processor bus timings are synchronous; that is, input setup/hold and
output delay with respect to the rising edge of a reference clock. The
reference clock is the CLKOUT output.
All other timing relationships can be derived from these values.
4
*
ico
5 + 5 x W) x T
*
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
2
= f
RFD
Characteristic
ref *
5, 6, 9,12, 13
)
2
*
ref
(MFD+2)
, where T
Measured at f
14
Table 47. PLL Electrical Specifications
,
15
16
ref
= 1/F
sys/2
sys/2
ref_crystal
DDPLL
value greater than the f
Preliminary
Max
NOTE
and V
= 1/F
ref_ext
SSPLL
Symbol
C
C
f
f
f
LCK
jitter
mod
UL
ico
= 1/F
and variation in crystal oscillator frequency
ref_1:1
sys/2
maximum specified value. Modulation
, and W = 1.57x10
1
- 3.8
- 1.7
Min
0.8
48
—
—
DD
and V
DDPLL
Freescale Semiconductor
-6
Max
4.1
2.0
.01
2.2
83
x 2(MFD + 2)
5
are valid to
% f
% f
% f
% f
MHz
Unit
sys/2
sys/2
sys/2
sys/2