mcf5274l Freescale Semiconductor, Inc, mcf5274l Datasheet - Page 33
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mcf5274l
Manufacturer Part Number
mcf5274l
Description
Mcf5275 Integrated Microprocessor Family Hardware
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MCF5274L.pdf
(76 pages)
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5.2
5.3
Figure 2
for the MCF5275.
Freescale Semiconductor
RCON
D26, D17, D16
D19, D18
D21
CLKMOD1,
CLKMOD0
D25, D24
JTAG_EN
shows a block diagram of the recommended circuit used to drive the reset configuration values
Chip Configuration Pins
Chip Configuration Circuit
Pin
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
Chip configuration
enable
Select chip
operating mode
Select external boot
device data port size
Select output pad
drive strength
Select clock mode
Select chip select /
address line
Selects BDM or
JTAG mode
Chip Configuration
Function
Table 20. Configuration Pin Descriptions
1 disabled
0 enabled
111 master
110 reserved
101 reserved
100 reserved
0xx reserved
00,11 external (32-bit)
10 external (8-bit)
01 external (16-bit)
1 Full
0 Partial
00 External clock mode (no
01 1:1 PLL mode
10 Normal PLL with
11 Normal PLL with crystal
00 PADDR[7:5] configured
10 PADDR7 configured as
01 PADDR[7:6] configured
11 PADDR[7:5] configured
0 BDM mode
1 JTAG mode
Preliminary
PLL)
external clock reference
clock reference
as A23-A21 (default)
CS6,
PADDR[6:5] as A22-A21
as CS[6:5],
PADDR5 as A21
as CS[6:4]
Pin State/Meaning
Active low: if asserted, then all
configuration pins must be driven
appropriately for desired operation
Value read defaults to 32-bit
VDDPLL must be supplied if a PLL
mode is selected
Comments
Chip Configuration
33