mcf5274l Freescale Semiconductor, Inc, mcf5274l Datasheet - Page 36

• Manufacturer Part Number: mcf5274l
• Description: Mcf5275 Integrated Microprocessor Family Hardware
• Manufacturer: Freescale Semiconductor, Inc

Design Recommendations
6.7.1.2
Table 22
connection configurations can be derived from this table.
36
SD_SRAS
SD_SCAS
SD_WE
SD_CS[1:0]
SD_CKE
BS[3:2]
DDR_CLKOUT
shows the generic address multiplexing scheme for SDRAM configurations. All possible address
Signal
Address Multiplexing
Address Pin Row Address Column Address
17
16
15
14
13
12
11
10
17
18
19
20
21
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
9
Synchronous row address strobe. Indicates a valid SDRAM row address is present and can be
latched by the SDRAM. SD_SRAS should be connected to the corresponding SDRAM
SD_SRAS. Do not confuse SD_SRAS with the DRAM controller’s SDRAM_CS[1:0], which
should not be interfaced to the SDRAM SD_SRAS signals.
Synchronous column address strobe. Indicates a valid column address is present and can be
latched by the SDRAM. SD_SCAS should be connected to the corresponding signal labeled
SD_SCAS on the SDRAM.
DRAM read/write. Asserted for write operations and negated for read operations.
Row address strobe. Select each memory block of SDRAMs connected to the MCF5275. One
SDRAM_CS signal selects one SDRAM block and connects to the corresponding CS signals.
Synchronous DRAM clock enable. Connected directly to the CKE (clock enable) signal of
SDRAMs. Enables and disables the clock internal to SDRAM. When CKE is low, memory can
enter a power-down mode where operations are suspended or they can enter self-refresh
mode. SD_CKE functionality is controlled by DCR[COC]. For designs using external
multiplexing, setting COC allows SD_CKE to provide command-bit functionality.
Column address strobe. For synchronous operation, BS[3:2] function as byte enables to the
SDRAMs. They connect to the DQM signals (or mask qualifiers) of the SDRAMs.
Bus clock output. Connects to the CLK input of SDRAMs.
Table 21. Synchronous DRAM Signal Connections
Table 22. Generic Address Multiplexing Scheme
17
16
15
14
13
12
11
10
17
18
19
20
21
9
16
17
18
19
20
0
1
2
3
4
5
6
7
8
Preliminary
Description
8-bit port only
8- and 16-bit ports only
32-bit port only
16-bit port only or 32-bit port with only 8
column address lines
16-bit port only when at least 9 column
address lines are used
Notes Related to Port Sizes
Freescale Semiconductor