st5451d STMicroelectronics, st5451d Datasheet - Page 53

• Manufacturer Part Number: st5451d
• Description: 2b1q U Interface Device
• Manufacturer: STMicroelectronics

Figure 11: Transformer Design.
Line Interface Circuit
It is very important, comply with ANSI, ETSI and
French standards, that the recommended line in-
terface circuit should be strictly adhered to. The
channel response and dynamic range of this cir-
cuit have been carefully designed as an integral
part of the overall signal processing system
to ensure that the performance require-
ments are met under all the specified loop
conditions. Deviations from this design are
likely to result in sub-optimal performance
or even total failure of the system on some
types of loops.
Turns Ratio: Np:Ns = 1:1.5.
Secondary Inductance: Lp 27mH.
Max leakage inductance: 100 H
Winding Resistances: 30 ohms (2.25Rp + Rs)
> 10 ohms.
Return Loss, at 40 kHz and load of 135 ohms: 26
dB. Saturation characteristics: THD –70dB when
tested with 50mA d.c. through the secondary and
a 40kHz sine-wave injected into the primary at a
level which generates, at the secondary, 5V
(R
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SHOTT
PULSE ENGINEERING
AIE
Table 11.
load
WINDING
WINDING
1-2 + 3-4
5-6 + 7-8
6-5, 8-7
= 135ohms).
1-2
3-4
(secondary)
LINE SIDE
120+120 Bifilar
INDUCTANCE
NUMBER OF
98 Single
62 Single
TURNS
12 mH
27 mH
120T
120T
WIRE GAUGE
RESISTANCE
less than 10
less than 5
#34 AWG
#36 AWG
#34 AWG
6
5
8
7
P-P
1.5:1
. .
. .
Board Layout
While the pins of the UID are well protected against
electrical misuse, it is recommended that the stand-
ard CMOS practise, of applying GND to the device
before any other connections are made, should al-
ways be followed. In applications where the printed
circuit card may be plugged into a hot socket with
power and clocks already present, an extra long
ground pin on the connector should be used. Great
care must be taken in the layout of the printed cir-
cuit board in order to preserve the high transmis-
sion performance of the STLC5411. To maximize
performance, do not use the philosophy of separat-
ing analog and digital grounds for chip. The 3 GND
pins should be connected together as close as pos-
sible to the pins, and the 2 VCC pins should be
strapped together. All ground connections to each
device should meet at a common point as close as
possible to the 3 GND pins to prevent the interac-
tion of ground return currents flowing through a
common bus impedance. Two decoupling capaci-
tors of 10 F and 0.1 F should be connected from
this common point to VCC pins as close as possi-
ble to the chip. Taking care with the board layout in
the following ways will also help prevent noise in-
jection into the receiver frontend and maximize the
transmission performances. Keep the crystal oscil-
lator components away from the receiver inputs
and use a shielded ground plane around these
components. Keep the device, the components
connected to LI+/LI- and the transformer as close
possible. Symmetrical layout for the line interface is
suggested.
1
98T
2
3
62T
4
DEVICE SIDE
(primary)
STLC5411
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