st5451d STMicroelectronics, st5451d Datasheet - Page 46

• Manufacturer Part Number: st5451d
• Description: 2b1q U Interface Device
• Manufacturer: STMicroelectronics

STLC5411
second line section to the first line section and
viceversa.
LFS Local febe select.
Please report to the figure 10. LFS is usefull in re-
port application to transfert or not the crc anoma-
lies (nebe) of a line section to the febe bit of the
same line section.
Configuration register TXB1
Significant only when format 3 selected.
( W/DSI Only)
After reset: 00H Time slot 0 selected.
B1X5-B1X0 Transmit B1 Time Slot Assignment
Those bits define the binary number of the trans-
mit B1 channel time-slot on Bx input. Time slot
are numbered from 0 to 63. The register content
is taken into account at each frame beginning.
Configuration register RXB1
Significant only when format 3 selected.
( W/DSI Only)
After reset: 00h Time slot 0 selected.
B1R5-B1R0 Receive B1 Time Slot Assignment
B1R5-B1R0 bits define the binary number of the
receive B1 channel time-slot on BR output. Time
slot are numbered from 0 to 63. The register con-
tent is taken into account at each frame begin-
ning.
Configuration register TXB2
Significant only when format 3 selected.
( W/DSI Only)
After reset: 01H Time slot 1 selected.
B2X5-B2X0 Transmit B2 Time Slot Assignment
Those bits define the binary number of the trans-
mit B2 channel time-slot on Bx input. Time slots
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RFS = 1: Transfert anomalies second section
RFS = 0: Transfert anomalies second section
RFS = 0: The computing febe takes in account
RFS = 1: The computing febe does not take in
–
-
-
–
-
-
first section and viceversa allowed.
first section and viceversa not allowed.
the local nebe.
account the local nebe.
B1R5 B2R4 B2R3 B2R2 B2R1 B2R0
B1X5 B1X4 B1X3 B1X2 B1X1 B1X0
B2X5 B2X4 B2X3 B2X2 B2X1 B2X0
are numbered from 0 to 63. The register content
is taken into account at each frame beginning.
Configuration register RXB2
Significant only when format 3 selected. ( W/DSI
Only)
After reset: 01H Time slot 1 selected.
B2R5-B2R0 Receive B2 Time Slot Assignment
Those bits define the binary number of the re-
ceive B2 channel time-slot on BR output. Time
slot are numbered from 0 to 63. The register con-
tent is taken into account at each frame begin-
ning.
Configuration register TXD
After reset:
lected)
Significant only when format 3 is selected with the
D channel selected in the multiplexed mode:
DX5-SX0 Transmit D channel Time Slot Assign-
ment
DX5-DX0 and SX1-SX0 bits define the binary
number of the transmit D channel time-slot. DX5-
DX0 bits define the binary number of the 8 bits
wide timeslot. Time slot are numbered from 0 to
63. Within this selected time slot, SX1,SX0 bits
define the binary number of the 2 bits wide time-
slot. Sub time-slots are numbered 0 to 3. The reg-
ister content is taken into account at each frame
beginning.
Configuration register RXD
After reset:
lected)
Significant only when format 3 is selected with the
D channel selected in multiplexed mode.
DR5-SR0 Receive D channel Time Slot Assign-
ment
DR5-DR0 and SR1-SR0 bits define the binary
number of the receive D channel time-slot. DR5-
DR0 bits define the binary number of the 8 bits
wide timeslot. Time slot are numbered from 0 to
63. Within this selected time slot., SR1,SR0 bits
define the binary number of the 2 bits wide time-
slot. Sub time-slots are numbered 0 to 3. The reg-
ister content is taken into account at each frame
beginning.
DR5
W mode 08H (sub time slot 0, time slot 2 se-
DX5
W mode 08H (sub time slot 0, time slot 2 se-
-
DR4
DX4
-
B2R5 B2R4 B2R3 B2R2 B2R1 B2R0
DX3
DR3
DX2
DR3
DX1
DR2
DX0
DR1
SR1
SX1
SX0
SR0