st5451d STMicroelectronics, st5451d Datasheet - Page 23

• Manufacturer Part Number: st5451d
• Description: 2b1q U Interface Device
• Manufacturer: STMicroelectronics

on Br is in the high impedance state.
A 24 ms timer is implemented in the UID. This
timer (when enabled) starts each time the sender
starts a byte sending and waits for a pre acknow-
ledgement.
C/I channel
The C/I channel is used for TXACT and RXACT
registers write and read operation. However, it is
possible to access to ACT registers by monitor
Figure 5: GCI Monitor channel messaging examples.
M
E
A
M
E
A
X
X
M1
Rea dy fo r
a message
M1
1st byt e
(M1)
Ready
for a message
M1
TWO BYTES MESSAGE ABORTED ON THE SECOND AND RETRANSMITTED
pre -ack
(M1)
1st byt e
(M1)
M1
M2
TWO BYTES MESSAGE - NORMAL TRANSMISSION
pre-a ck
(M1)
ack
(M1)
(M2)
2nd byte
M2
M2
pre -ack
(M2)
E & A BITS TIMING
ack
(M1)
X
2n d byte
(M2)
M2
ab ort
(M2)
(X)
channel: this access is controled by the CID bit in
CR2 register.
The four bits code (C1,C2,C3,C4) of TXACT reg-
ister can be loaded in the UID by writing perma-
nently this code in the C/I channel time-slot on Bx
input every GCI frames. The UID takes into ac-
count the received code when it has been re-
ceived two consecutive times identical. When a
status change occurs in the RXACT register, the
new (C1,C2,C3,C4) code is sent in the C/I chan-
nel time-slot on Br output every GCI frames. This
3r d byte? ?
(M2)
pr e-ac k
X
Read y for
retr ansmission
X
EOM
(or ab ort ack )
X
ack
(M2)
3rd byt e??
(X)
X
X
pre- ack ??
(X)
EOM
M1
X
1st byte
(M1)
Rea dy for
a new messag e
M1
pre -ack
(M1)
STLC5411
M2
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