st5080d STMicroelectronics, st5080d Datasheet - Page 18

• Manufacturer Part Number: st5080d
• Description: Piafe Programmable Isdn Audio Front End
• Manufacturer: STMicroelectronics

ST5080A
CONTROL REGISTER CR0
First byte of a READ or a WRITE instruction to
Control Register CR0 is as shown in TABLE 1.
Second byte is as shown in TABLE 2.
Master Clock Frequency Selection
A master clock must be provided to PIAFE for op-
eration of filter and coding/decodingfunctions.
In COMBO I/II mode, MCLK frequency can be
either 512 kHz, 1.536 MHz, 2.048 MHz or 2.56
MHz.
Bit F1 (7) and F0 (6) must be set during initializa-
tion to select the correct internal divider.
In GCI mode, MCLK must be either 1.536MHz or
MSB is always the first PCM bit shifted in or out of PIAFE.
Digital Interface timing
Bit DN=0 (3) selects digital interface in delayed
timing mode while DN=1 selects non delayed
data timing.
In GCI mode, bit DN is not significant.
After reset and if COMBO I/II mode is selected,
delayed data timing is selected.
Digital Interface format
Bit FF=0 (2) selects digital interface in Format 1
where B1 and B2 channel are consecutive. FF=1
selects Format 2 where B1 and B2 channel are
separated by two bits. (see digital interface format
section).
In GCI mode, bit FF is not significant.
56+8 selection
Bit ’B7’ (1) selects capability for PIAFE to take
into account only the seven most significant bits
of the PCM data byte selected.
When ’B7’ is set, the LSB bit on D
LSB bit on D
lows connection of an external ”in band” data
generator directly connected on the Digital Inter-
face.
Digital loopback
Digital loopback mode is entered by setting DL
bit(0) equal 1.
In Digital Loopback mode, data written into Re-
ceive PCM Data Register from the selected re-
ceived time-slot is read-back from that Register in
18/32
Vin = + full scale
Vin = 0 V
Vin = - full scale
X
is high impedance. This function al-
1
1
0
0
msb
0
1
1
0
0
1
1
0
R
Mu 255 law
is ignored and
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
lsb
0
1
1
0
1
1
0
0
msb
2.048MHz.
512KHz and 2.56MHz are not allowed.
Default value is 1.536 MHz for both modes.
Any clock different from the default one must be
selected prior a Power-Up instruction for both
modes.
Coding Law Selection
Bits MA (5) and IA (4) permit selection of Mu-255
law or A law coding with or without even bit inver-
sion.
After power on initialization, the Mu-255 law is se-
lected.
the selected transmit time-slot on D
selected with Register CR1.
No PCM decoding or encoding takes place in this
mode. Transmit and Receive amplifier stages are
muted.
CONTROL REGISTER CR1
First byte of a READ or a WRITE instruction to
Control Register CR1 is as shown in TABLE 1.
Second byte is as shown in TABLE 3.
Hands-free I/Os selection
Bit HFE set to one enables HFI, HFO pins for
connection of an external handfree circuit such as
TEA 7540. HFO is an analog output that provides
the receive voice signal. 0 dBMO level on that
output is 0.491 Vrms (1.4V
high impedance input (10 K
send back the processed receive signal to the
Loudspeaker. 0 dBMO level on that input is
0.491Vrms.
Anti-larsen selection
Bit ALE set to one enables on-chip antilarsen and
squelch effect system.
Latch output control
Bit DO controls directly logical status of latch out-
put LO: ie, a ”ZERO” written in bit DO puts output
LO in high impedance, a ”ONE” written in bit DO
sets output LO to zero.
True A law even bit
0
1
1
0
1
0
0
1
inversion
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
lsb
0
1
1
0
0
1
1
0
msb
A law without even bit
1
0
0
1
pp
). HFI is an analog
1
0
0
1
inversion
typ.) intended to
1
0
0
1
X
. Time slot is
1
0
0
1
1
0
0
1
1
0
0
1
lsb
1
0
0
1