cs4239 Cirrus Logic, Inc., cs4239 Datasheet - Page 31

• Manufacturer Part Number: cs4239
• Description: Crystalclear? Ortable Isa Audio System Logic
• Manufacturer: Cirrus Logic, Inc.

DIRECT MAPPED REGISTERS
The first two WSS Codec registers provide indi-
rect accessing to more codec registers via an
index register. The other two registers provide
status information and allow audio data to be
transferred to and from the WSS Codec without
using DMA cycles or indexing.
Note that register defaults are listed in binary
form with reserved bits marked with ’x’ to indi-
cate unknown. Bits in the default marked with
an ’e’ indicate that the bit is initialized through
E
parts, these reserved bits must be written as 0,
and must be masked off when the register is
read. The current value read for reserved bits is
not guaranteed on future revisions. While the re-
served bits are listed as "res" in the bit position,
"rbc" is used for "reserved, backwards compat-
ible" for bits that were used on previous chips,
but are no longer required on this chip. These
bits are read/writable but should generally be set
to 0 for backwards compatibility.
IA3-IA0
IA4
DS253PP2
Index Address Register
(WSSbase+0, R0)
2
INIT
D7
PROM. To maintain compatibility with future
MCE
D6
TRD
D5
Index Address: These bits define the
address of the indirect register ac-
cessed by the Indexed Data register
(R1). These bits are read/write.
Allows access to indirect registers 16
served and must be written as zero.
- 31. In MODE 1, this bit is re-
D4
IA4
D3
IA3
D2
IA2
D1
IA1
D0
IA0
TRD
MCE
INIT
Immediately after RESET (and once the WSS
Codec has left the INIT state), the state of this
register is: 010x0000 (binary - where ’x’ indi-
cates unknown).
During initialization and software power down
(PDWN in CTRLbase+7), this register cannot be
written and always reads 10000000 (80h)
ID7-ID0
Indexed Data Register
(WSSbase+1, R1)
D7
ID7
D6
ID6
CrystalClear Portable ISA Audio System
D5
ID5
Transfer Request Disable: This bit,
when set, causes DMA transfers to
cease when the INT bit of the Status
Register (R2) is set. Independent for
playback and capture interrupts.
0 - Transfers Enabled (playback and
1 - Transfers Disabled (playback and
Mode Change Enable: This bit must
be set whenever the current mode
of the WSS Codec is changed. The
Data Format (I8, I28) and Interface
Configuration (I9) registers CANNOT
be changed unless this bit is set.
The exceptions are CEN and PEN
which can be changed "on-the-fly".
The DAC output is muted when
MCE is set.
read as 1 when the Codec is in a
state in which it cannot respond to
parallel interface cycles. This bit is
read-only.
Indexed Data register: These bits are
the indirect register referenced by
the Indexed Address register (R0).
WSS Codec Initialization: This bit is
capture DRQs occur uninhibited)
capture DRQ only occur if INT bit
is 0)
D4
ID4
TM
D3
ID3
D2
ID2
D1
ID1
CS4239
D0
ID0
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