EMD56164P Emlsi Inc., EMD56164P Datasheet - Page 21

• Manufacturer Part Number: EMD56164P
• Description: 256m 16m X 16 Mobile Ddr Sdram
• Manufacturer: Emlsi Inc.

Preliminary
EMD56164P
256M: 16M x 16 Mobile DDR SDRAM
SELF REFRESH
The SELF REFRESH command can be used to retain data in the Mobile DDR SDRAM, even if the rest of the system
is powered down. When in the self refresh mode, the Mobile DDR SDRAM retains data without external clocking. The
SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW). All com-
mand and address input signals except CKE are “Don’t Care” during SELF REFRESH.
During SELF REFRESH, the device is refreshed as identified in the external mode register (see PASR setting). For
the full array refresh, all four banks are refreshed simultaneously with the refresh frequency set by an internal self
refresh oscillator. This oscillator changes due to the temperature sensor’s input. As the case temperature of the Mobile
DDR SDRAM increases, the oscillation frequency will change to accommodate the change of temperature. This hap-
pens because the DRAM capacitors lose charge faster at higher temperatures. To ensure efficient power dissipation
during self refresh, the oscillator will change to refresh at the slowest rate possible to maintain the devices data.
The procedure for exiting SELF REFRESH requires a sequence of commands. First, CK must be stable prior to CKE
going back HIGH. Once CKE is HIGH, the Mobile DDR SDRAM must have NOP commands issued for tXSR is
required for the completion of any internal refresh in progress.
Self Refresh
CKB
CK
Self
Command
Active
CMD
Refresh
CKE = High
t
XSR
t
IS
DEEP POWER-DOWN
The operating mode deep power-down achieves maximum power reduction by eliminating the power of the whole
memory array of the device. Array data will not be retained once the device enters deep power-down mode.
This mode is entered by having all banks idle then
and WEB held LOW with RASB and CASB held HIGH at the
CSB
rising edge of the clock, while CKE is LOW. This mode is exited by asserting CKE HIGH.
Rev 0.0
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