EMD28164PA Emlsi Inc., EMD28164PA Datasheet - Page 3

• Manufacturer Part Number: EMD28164PA
• Description: 128m 8m X 16 Mobile Ddr Sdram
• Manufacturer: Emlsi Inc.

Table 2: Pad Description
CK, /CK
CKE
/CS
/RAS, /CAS, /WE
LDM, UDM
BA0, BA1
A0 - A11
DQ0-DQ15
LDQS, UDQS
VDD
VSS
VDDQ
VSSQ
Symbol
Supply Power Supply
Supply Ground
Supply I/O Power Supply
Supply I/O Ground
Input
Input
Input
Input
Input
Input
Input
Type
I/O
I/O
Clock : CK and /CK are differential clock inputs. All address and control input signals are sampled on
the crossing of the positive edge of CK and negative edge of /CK. Input and output data is referenced to
the crossing of CK and /CK(both directions of crossing). Internal clock signals are derived from CK//CK.
Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input
buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF
REFRESH operation(all banks idle), or ACTIVE POWER-DOWN(row ACTIVE in any bank). CKE is
synchronous for all functions except for SELF REFRESH EXIT, which is achieved asynchronously.
Input buffers, excluding CK, /CK and CKE, are disabled during power-down and self refresh mode
which are contrived for low standby power consumption.
Chip Select : /CS enables (registered LOW) and disables (registered HIGH) the command decoder. All
commands are masked when /CS is registered HIGH. /CS provides for external bank selection on sys-
tems with multiple banks. /CS is considered part of the command code.
Command Inputs: /CAS, /RAS, and /WE(along with /CS) define the command being entered.
Input Data Mask : DM is an input mask signal for write data. Input data is masked when DM is sampled
HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS.
Although DM pins are input-only, the DM loading matches the DQ and DQS loading. For x16 devices,
LDM corresponds to the data on DQ0-DQ7, UDM corresponds to the data on DQ8-DQ15.
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRECHARGE
command is being applied.
Address Inputs: provide the row address for ACTIVE commands, and the column address and AUTO
PRECHARGE bit for READ / WRITE commands, to select one location out of the memory array in the
respective bank. The address inputs also provide the op-code during a MODE REGISTER SET com-
mand.
Data Bus: Input / Output
Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered with
write data. Used to capture write data. For x16 device, LDQS corresponds to the data on DQ0-DQ7,
UDQS corresponds to the data on DQ8-DQ15.
3
Descriptions
128M: 8M x 16 Mobile DDR SDRAM
EMD28164PA
Rev 1.0