S25FL032A Meet Spansion Inc., S25FL032A Datasheet - Page 23

• Manufacturer Part Number: S25FL032A
• Description: 32 Megabit Cmos 3.0 Volt Flash Memory With 50 Mhz Spi Bus Interface
• Manufacturer: Meet Spansion Inc.

9.9
9.10
July 2, 2007 S25FL032A_00_C2
Sector Erase (SE)
Bulk Erase (BE)
The Sector Erase (SE) command sets all bits at all addresses within a specified sector to a logic 1. A WREN
command is required prior to writing the PP command.
The host system must drive CS# low, and then write the SE command plus three address bytes on SI. Any
address within the sector (see
driven low for the entire duration of the SE sequence. The command sequence is shown in
Table 9.4 on page
The host system must drive CS# high after the device has latched the 8th bit of the SE command, otherwise
the device does not execute the command. The SE operation begins as soon as CS# is driven high. The
device internally controls the timing of the operation, which requires a period of t
be read to check the value of the Write In Progress (WIP) bit while the SE operation is in progress. The WIP
bit is 1 during the SE operation, and is 0 when the operation is completed. The device internally resets the
Write Enable Latch to 0 before the operation completes (the exact timing is not specified).
The device does not execute an SE command that specifies a sector that is protected by the Block Protect
bits (BP2:BP0) (see
The Bulk Erase (BE) command sets all the bits within the entire memory array to logic 1s. A WREN command
is required prior to writing the PP command.
The host system must drive CS# low, and then write the BE command on SI. CS# must be driven low for the
entire duration of the BE sequence. The command sequence is shown in
on page
The host system must drive CS# high after the device has latched the 8th bit of the CE command, otherwise
the device does not execute the command. The BE operation begins as soon as CS# is driven high. The
device internally controls the timing of the operation, which requires a period of t
be read to check the value of the Write In Progress (WIP) bit while the BE operation is in progress. The WIP
bit is 1 during the BE operation, and is 0 when the operation is completed. The device internally resets the
Write Enable Latch to 0 before the operation completes (the exact timing is not specified).
The device only executes a BE command if all Block Protect bits (BP2:BP0) are 0 (see
on page
CS#
SCK
SI
SO
26.
12). Otherwise, the device ignores the command.
Hi-Z
Mode 3
Mode 0
26.
Table 7.1 on page
D a t a
0
Figure 9.9 Sector Erase (SE) Command Sequence
Table 7.1 on page
1
2
S h e e t
Command
3
12).
S25FL032A
4
5
12) is a valid address for the SE command. CS# must be
6
7
MSB
23 22
8
9
24-bit Address
21
10
28
Figure 9.10
3
29
2
SE
BE
30
1
. The Status Register may
. The Status Register may
31
0
and
Table 7.1
Table 9.4
Figure 9.9
and
23