S25FL032A Meet Spansion Inc., S25FL032A Datasheet - Page 11

• Manufacturer Part Number: S25FL032A
• Description: 32 Megabit Cmos 3.0 Volt Flash Memory With 50 Mhz Spi Bus Interface
• Manufacturer: Meet Spansion Inc.

7. Device Operations
7.1
7.2
7.3
7.4
7.5
July 2, 2007 S25FL032A_00_C2
Byte or Page Programming
Sector Erase / Bulk Erase
Monitoring Write Operations Using the Status Register
Active Power and Standby Power Modes
Status Register
All Spansion SPI devices (S25FL-A) accept and output data in bytes (8 bits at a time).
Programming data requires two commands: Write Enable (WREN), which is one byte, and a Page Program
(PP) sequence, which consists of four bytes plus data. The Page Program sequence accepts from 1 byte up
to 256 consecutive bytes of data (which is the size of one page) to be programmed in one operation.
Programming means that bits can either be left at 0, or programmed from 1 to 0. Changing bits from 0 to 1
requires an erase operation. Before this can be applied, the bytes of the memory need to be first erased to all
1’s (FFh) before any programming.
The Sector Erase (SE) and Bulk Erase (BE) commands set all the bits in a sector or the entire memory array
to 1. While bits can be individually programmed from a 1 to 0, erasing bits from 0 to 1 must be done on a
sector-wide (SE) or array-wide (BE) level.
The host system can determine when a Write Status Register, program, or erase operation is complete by
monitoring the Write in Progress (WIP) bit in the Status Register. The Read from Status Register command
provides the state of the WIP bit.
The device is enabled and in the Active Power mode when Chip Select (CS#) is Low. When CS# is high, the
device is disabled, but may still be in the Active Power mode until all program, erase, and Write Status
Register operations have completed. The device then goes into the Standby Power mode, and power
consumption drops to I
inadvertent signals. After writing the DP command, the device ignores any further program or erase
commands, and reduces its power consumption to I
The Status Register contains the status and control bits that can be read or set by specific commands
(Table 9.2, S25FL032A Status Register on page
Write In Progress (WIP): Indicates whether the device is performing a Write Status Register, program or
erase operation.
Write Enable Latch (WEL): Indicates the status of the internal Write Enable Latch.
Block Protect (BP2, BP1, BP0): Non-volatile bits that define memory area to be software-protected
against program and erase commands.
Status Register Write Disable (SRWD): Places the device in the Hardware Protected mode when this bit
is set to 1 and the W# input is driven low. In this mode, the non-volatile bits of the Status Register (SRWD,
BP2, BP1, BP0) become read-only bits.
SB
D a t a
. The Deep Power Down (DP) command provides additional data protection against
S h e e t
S25FL032A
20):
DP
.
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