LDS-L9D340G64BG2 LOGIC Devices Incorporated, LDS-L9D340G64BG2 Datasheet - Page 126

• Manufacturer Part Number: LDS-L9D340G64BG2
• Description: 4.0 Gb, Ddr3, 64 M X 64 Integrated Module Imod
• Manufacturer: LOGIC Devices Incorporated

LOGIC Devices Incorporated
F
F
IGURE
IGURE
DQS, DQS#
Command 1
DQS, DQS#
C ommand
Add ress 3
Add ress
79 - N
80 - WRITE (BL8)
C K#
DM
CK
DQ
CK#
DQ 4
CK
WRITE
Vali d
T0
WRITE
Vali d
T0
ONCONSECUTIVE
NOP
T1
Notes:
Notes:
NOP
T1
www.logicdevices.com
NOP
T2
1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2.
3. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and MR0[12] = 1 during the WRITE command at T0.
4. DI n = data-in for column n.
5. RL = 5 (AL = 0, CL = 5), WL = 5 (AL = 0, CWL = 5).
1. DI n (or b) = data-in for column n (or column b).
2. Seven subsequent elements of data-in are applied in the programmed order following DO n.
3. Each WRITE command may be to any bank.
4. Shown for WL = 7 (CWL = 7, AL = 0).
t
data shown at T9.
The READ command at Ta0 can be either BC4 or BL8, depending on MR0[1:0] and the A12 status at Ta0.
WTR controls the WRITE-to-READ delay to the same device and starts with the first rising clock edge after the last write
WL = C WL + AL = 7
TO
NOP
NOP
T3
T2
WRITE
READ (BL8)
WL = 5
NOP
T4
NOP
T3
TO
WRITE
Vali d
T5
WRITE
NOP
T4
T6
NOP
t WPRE
NOP
NOP
T7
DI
T5
n
DI
n
4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD)
n + 1
DI
n + 1
DI
WL = C WL + AL = 7
n + 2
T8
NOP
DI
126
n + 2
NOP
T6
DI
n + 3
DI
n + 4
NOP
T9
DI
n + 3
DI
n + 5
DI
n + 4
NOP
T7
DI
PRELIMINARY INFORMATION
T10
n + 6
NOP
DI
n + 5
n + 7
DI
DI
NOP
T11
n + 6
NOP
T8
DI
High Performance, Integrated Memory Module Product
n + 7
DI
T12
NOP
DI
b
t WPST
Indicates a Break in
Time Scale
b + 1
NOP
T9
DI
T13
NOP
b + 2
DI
b + 3
DI
NOP
T10
T14
NOP
b + 4
DI
b + 5
t WTR 2
DI
Transitioning Data
T15
NOP
b + 6
DI
L9D340G64BG2
Transitioning Data
NOP
T11
b + 7
DI
Jun 08, 2010 LDS-L9D340G64BG2-B
NOP
T16
READ
Ta0
Vali d
Don ’t Care
Don't Care
NOP
T17