LDS-L9D340G64BG2 LOGIC Devices Incorporated, LDS-L9D340G64BG2 Datasheet - Page 124

• Manufacturer Part Number: LDS-L9D340G64BG2
• Description: 4.0 Gb, Ddr3, 64 M X 64 Integrated Module Imod
• Manufacturer: LOGIC Devices Incorporated

LOGIC Devices Incorporated
F
IGURE
Command 1
DQS, DQS#
DQS, DQS#
DQS, DQS#
Address 2
76 - W
CK#
DQ 3
DQ 3
DQ 3
CK
t DQSS (NOM)
t DQSS (MIN)
t DQSS (MAX)
WRITE
Bank,
Col n
RITE
T0
B
Notes:
URST
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NOP
T1
1. NOP commands are shown for ease of illustration; other commands may be valid at these
2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during the
3. DI n = data-in for column n.
4. BL8, WL = 5 (AL = 0, CWL = 5).
5.
6.
times.
WRITE command at T0.
t
t
ends when DQS no longer drives LOW and DQS# no longer drives HIGH.
WL = AL + CWL
DQSS must be met at each rising clock edge.
WPST is usually depicted as ending at the crossing of DQS, DQS#; however,
NOP
T2
NOP
T3
t DQSH
NOP
T4
t DQSH
t WPRE
4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD)
t WPRE
t DQSH
t DQSL
t DQSS t DSH
t DQSL
t WPRE
t DSS
124
DI
n
t DSS
t DQSH
t DQSL
NOP
DI
T5
n
t DQSS
t DQSH
t DSH
n + 1
DI
DI
n
t DQSH
t DQSL
n + 1
DI
t DQSL
t DSS
n + 2
n + 1
DI
DI
PRELIMINARY INFORMATION
t DSS
t DQSH
t DQSL
NOP
n + 2
T6
DI
t DSH
t DQSH
t DSH
n + 3
n + 2
DI
DI
t DQSH
t DQSL
n + 3
DI
t DQSL
High Performance, Integrated Memory Module Product
n + 4
t DSS
n + 3
DI
DI
t DSS
t DQSH
t DQSL
n + 4
NOP
T7
DI
t DSH
t DQSH
t DSH
n + 4
n + 5
DI
DI
t DQSH
t DQSL
n + 5
DI
t DQSL
n + 6
t DSS
n + 5
DI
DI
t DSS
t DQSH
t DQSL
n + 6
NOP
T8
DI
t DSH
t DQSH
t DSH
n + 7
n + 6
DI
DI
t DQSH
t WPST
t DQSL
n + 7
Transitioning Data
DI
t WPST
t DQSL
t DSS
n + 7
DI
t DSS
t
t WPST
t DQSL
WPST actually
NOP
T9
L9D340G64BG2
Jun 08, 2010 LDS-L9D340G64BG2-B
Don ’t Care
T10
NOP