ds3171n Maxim Integrated Products, Inc., ds3171n Datasheet - Page 29

• Manufacturer Part Number: ds3171n
• Description: Ds3171, Ds3172, Ds3173, Ds3174 Single/dual/triple/quad Ds3/e3 Single-chip Transceivers
• Manufacturer: Maxim Integrated Products, Inc.

PIN NAME
RNEGn /
RPOSn /
RLCLKn
RDATn
RLCVn
RXPn
RXNn
TYPE
Iad
Iad
Ia
Ia
I
Receive Positive analog
RXPn: This pin and the RXNn pin form a differential AMI input which is coupled to the outbound
75Ω coaxial cable through a 2:1 step-up transformer
RX LIU is enabled and is ignored when the LIU is disabled.
o
o
Receive Negative analog
RXNn: This pin and the RXPn pin form a differential AMI input which is coupled to the outbound
75Ω coaxial cable through a 2:1 step-up transformer
LIU is enabled and is ignored when the LIU is disabled.
o
o
Receive Line Clock Input
RLCLKn: This clock is typically used for the reference clock for the RPOSn / RDATn, RNEGn /
RLCVn signals but can also be used as the reference clock for the RSERn, RSOFOn / RDENn,
TSOFIn, TSERn, TSOFOn / TDENn, TPOSn / TDATn and TNEGn signals. This input is ignored
when the LIU is enabled.
This input signal can be inverted.
o
o
Receive Positive AMI / Data
RPOSn: When the port line is configured for B3ZS, HDB3 or AMI mode and the LIU is disabled,
a high on this pin indicates that a positive pulse has been detected using an external LIU. The
signal is sampled on the positive clock edge of the referenced clock pin if the clock pin signal is
not inverted, otherwise it is sampled on the falling edge of the clock. The signal is typically
referenced to the RLCLKn line clock input pins, but it can be referenced to the RCLKOn output
pins.
This input signal can be inverted.
RDATn: When the port line interface is configured for UNI mode, the un-encoded receive signal
is input on this pin. The signal is sampled on the positive clock edge of the referenced clock pin
if the clock pin signal is not inverted, otherwise it is sampled on the falling edge of the clock.
The signal is typically referenced to the RLCLKn line clock input pins, but it can be referenced
to the RCLKOn output pins.
This input signal can be inverted.
o
o
Receive Negative AMI / Line Code Violation / Line OH Mask input
RNEGn: When the port line is configured for B3ZS, HDB3 or AMI mode and the LIU is disabled,
a high on this pin indicates that a negative pulse has been detected using an external LIU. The
signal is sampled on the positive clock edge of the referenced clock pin if the clock pin signal is
not inverted, otherwise it is sampled on the falling edge of the clock. The signal is typically
referenced to the RLCLKn line clock input pins, but it can be referenced to the RCLKOn output
pins.
This input signal can be inverted.
o
o
RLCVn: When the port line interface is configured for UNI mode, the BPV counter in the
encoder/decoder block is incremented each clock when this signal is high. The signal is
sampled on the positive clock edge of the referenced clock pin if the clock pin signal is not
inverted, otherwise it is sampled on the falling edge of the clock. The signal is typically
referenced to the RLCLKn line clock input pins, but it can be referenced to the RCLKOn output
pins.
This input signal can be inverted.
DS3: 44.736 Mbps +20ppm
E3: 34.368 Mbps +20ppm
DS3: 44.736 Mbps +20ppm
E3: 34.368 Mbps +20ppm
DS3: 44.736 MHz +20 ppm
E3: 34.368 MHz +20 ppm
DS3: 44.736 Mbps +20ppm
E3: 34.368 Mbps +20ppm
DS3: 44.736 Mbps +20ppm
E3: 34.368 Mbps +20ppm
29
PIN DESCRIPTION
(Figure
(Figure
1-1). This input is used when the
1-1). This input is used when the