ds3171n Maxim Integrated Products, Inc., ds3171n Datasheet - Page 166
![no-image](/images/no-image-200.jpg)
ds3171n
Manufacturer Part Number
ds3171n
Description
Ds3171, Ds3172, Ds3173, Ds3174 Single/dual/triple/quad Ds3/e3 Single-chip Transceivers
Manufacturer
Maxim Integrated Products, Inc.
Datasheet
1.DS3171N.pdf
(234 pages)
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 13 to 8: Transmit FEAC Code B (TFCB[5:0]) – These six bits are the transmit FEAC code B data to be
stored inserted into codeword B. TFCB[5] is the LSB (last bit transmitted) of the FEAC code (C[6]), and TFCB[0] is
the MSB (first bit transmitted) of the FEAC code (C[1]).
Bits 5 to 0: Transmit FEAC Code A (TFCA[5:0]) – These six bits are the transmit FEAC code A data to be stored
inserted into codeword A. TFCA[5] is the LSB (last bit transmitted) of the FEAC code (C[6]), and TFCA[0] is the
MSB (first bit transmitted) of the FEAC code (C[1]).
Register Name:
Register Description:
Register Address:
Bit #
Name
Bit #
Name
Bit 0: Transmit FEAC Idle (TFI) – When 0, the Transmit FEAC processor is sending a FEAC codeword. When 1,
the Transmit FEAC processor is sending an Idle signal (all ones).
Register Name:
Register Description:
Register Address:
Bit #
Name
Bit #
Name
Bit 0: Transmit FEAC Idle Latched (TFIL) – This bit is set when the TFI bit transitions from 0 to 1. Note:
Immediately after a reset, this bit will be set to one.
15
15
15
--
--
--
--
--
--
0
7
0
7
7
14
14
14
--
--
--
--
--
--
0
6
0
6
6
FEAC.TFDR
Transmit FEAC Data Register
(0,2,4,6)C2h
FEAC.TSR
FEAC Transmit Status Register
(0,2,4,6)C4h
FEAC.TSRL
FEAC Transmit Status Register Latched
(0,2,4,6)C6h
TFCB5
TFCA5
13
13
13
--
--
--
--
0
5
0
5
5
TFCB4
TFCA4
12
12
12
0
0
--
--
--
--
4
4
4
166
TFCB3
TFCA3
11
11
11
--
--
--
--
0
3
0
3
3
TFCB2
TFCA2
10
10
10
--
--
--
--
0
2
0
2
2
TFCB1
TFCA1
--
--
--
--
9
0
1
0
9
1
9
1
TFCB0
TFCA0
TFIL
TFI
--
--
8
0
0
0
8
0
8
0
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