st2032a Sitronix Technology Corporation, st2032a Datasheet - Page 25

• Manufacturer Part Number: st2032a
• Description: 8 Bit Microcontroller With 32k Bytes Rom
• Manufacturer: Sitronix Technology Corporation

13.2 Tone Generator
13.2.1 General Description
The tone frequency is decided by PSGCK and 12-bit
programmable divider (PSG[11~0]). Please refer to
Ver 2.4
Address Name
Address Name
$010
$012
$013
$016
$017
$017
$011
Bit 3~0: VOL0[3~0] : PSG channel 0 volume control bit
Bit 7~4: VOL1[3~0] : PSG channel 1 volume control bit
Note: If single channel is enable, then PSG volume control can be double. (16
PSG0L
PSG0H
PSG1L
PSG1H
PSGC
VOL
VOL
0000 = No sound output
0001 = 1/16 volume
0100 = 4/16 volume
1000 = 8/16 volume
1111 = Maximum volume
0000 = No sound output
0001 = 1/16 volume
0100 = 4/16 volume
1000 = 8/16 volume
1111 = Maximum volume
+ 16 = 32 level volume control)
:
:
:
:
:
:
R/W
R/W
W
W
W
W
W
W
W
W
Frequency of Channel 0 Tone = PSGCK/(1000H-PCH0[11~0])/2
PSG0[11~8]
PSG0[7~0]
PSG0[7] PSG0[6] PSG0[5] PSG0[4] PSG0[3]
PSG1[7] PSG1[6] PSG1[5] PSG1[4] PSG1[3]
VOL1[3] VOL1[2] VOL1[1] VOL1[0] VOL0[3]
VOL1[3] VOL1[2] VOL1[1] VOL1[0] VOL0[3] VOL0[2] VOL0[1] VOL0[0]
PSGCK
Bit 7
Bit 7
C0EN
LOAD
-
-
-
-
TABLE 13-2 PSG Volume Control Register (VOL)
FIGURE 13-3 Tone Generator Channel 0
PCK[2]
PCK[2]
Bit 6
Bit 6
(PSGCK must >= 20K Hz)
TABLE 13-1 Summary Of PSG Registers
-
-
C0[11~8]
C0[7~0]
CLOCK
(PSGCK must >= 320K Hz)
Enable
Latch
(PSGCK must >= 20K Hz)
(PSGCK must >= 320K Hz)
12 Bit Auto-reload Up Counter
PCK[1]
PCK[1]
Bit 5
Bit 5
-
-
Channel 0
PCK[0]
PCK[0]
25/54
Bit 4
Bit 4
-
-
FIGURE 13-3 and.FIGURE 13-4.
OUTPUT
PSG0[11] PSG0[10] PSG0[9] PSG0[8]
PSG1[11] PSG1[10] PSG1[9] PSG1[8]
DMD[1]
Bit 3
PRBS
Bit 3
PSG0[2] PSG0[1] PSG0[0] 0000 0000
PSG1[2] PSG1[1] PSG1[0] 0000 0000
VOL0[2]
Bit 2
DMD[0]
C1EN
Bit 2
Tone out
Bit 1
VOL0[1] VOL0[0]
C0EN
Bit 1
INH
Bit 0
DACE=0
DACE=1
Bit 0
0000 0000
Default
- 000 0000
- 000 0000
- - - - 0000
- - - - 0000
0000 0000
Default
ST2032A
9/13/07