st2032a Sitronix Technology Corporation, st2032a Datasheet
st2032a
Related parts for st2032a
st2032a Summary of contents
Page 1
... The ST2032A is a 8-bit microcontroller designed with CMOS silicon gate technology. This single chip microcontroller is useful for translator, databank and other consumer applications. It integrates with SRAM, mask ROM, LCD controller/driver, Ver 2.4 8 BIT Microcontroller with 32K bytes ROM n n ...
Page 2
... ST2032A ...
Page 3
... ST2032A Unit: μ m PAD PITCH X Y 105.1 117.95 0 120 0 120 0 120 0 120 0 120 0 120 0 120 0 120 0 120 0 120 ...
Page 4
... ST2032A PAD PITCH X Y -120 0 -120 0 -120 -20 -13.25 -134 0 -120 0 -120 0 -120 0 -120 0 -120 0 -120 0 -120 0 -120 ...
Page 5
... PVCC Ver 2.4 -1029.75 1184.9 5/54 ST2032A 120 0 9/13/07 ...
Page 6
... LOW VOLTAGE DETECTOR PORT Ver 2 LCD RAM DAC PSG 6/54 CPU ROM CLOCK TIMER GENERATOR ST2032A 9/13/07 ...
Page 7
... High frequency crystal/resonator oscillator output pin. Connect to external crystal/resonator. P Ground pin P Power supply pin, Analogy Power supply pin I/O Connect to booster capacitor positive(+) terminal I/O Connect to booster capacitor negative(-) terminal O Voltage output of booster circuit I Chip test function. Leave it open. I PSG power input 7/54 ST2032A Description 9/13/07 ...
Page 8
... Bit 4 Bit 8/54 Bit 2 Bit Bit Decimal mode flag 1 = Decimal mode 0 = Binary mode Bit Interrupt disable flag 1 = Interrupt disable 0 = Interrupt enable Bit Zero flag 1 = Zero 0 = Non zero Bit Carry flag 1 = Carry 0 = Non carry ST2032A Bit 0 C 9/13/07 ...
Page 9
... F I 8.1 Memory map ST2032A builds in 32K bytes ROM and 1K bytes RAM. The internal ROM can be used as data memory or program memory. PRR is the Program ROM Bank Register. The logical program ROM address is from $4000 to $7FFF(16K bytes) is for logical program ROM address. 0000 ...
Page 10
... LSEL[0] CTR[2] CTR[1] CTR[0] - LCK[2] LCK[1] LCK[0] IRT1 IRT0 IRDAC IRX IET1 IET0 IEDAC IEX ST2032A Bit1 Bit0 - PRR0 Default 1111 1111 1111 1111 1111 1111 0000 0000 0000 0000 0000 0000 100 - - - - - 0000 0000 - - - - 0000 0000 0000 000 - - - - - ...
Page 11
... After the system has been operating, a low on this line at least of two clock cycles will cease ST2032A activity. When a positive edge is detected, there is an initialization sequence lasting six clock cycles. Then the interrupt mask flag is set, the decimal mode is cleared and the program counter will loaded with the restart vector from locations $7FFC (low byte) and $7FFD (high byte) ...
Page 12
... DAC time out interrupt enable 0 = DAC time out interrupt disable Bit 0: IEX: INTX Interrupt Enable bit 1 = INTX edge interrupt enable 0 = INTX edge interrupt disable 12/54 Bit 2 Bit 1 Bit 0 Default IRT0 IRDAC IRX - - 00 0000 Bit 2 Bit 1 Bit 0 Default IET0 IEDAC IEX - - 00 0000 ST2032A 9/13/07 ...
Page 13
... 10.1 Description ST2032A can supply total 24 GPIOs divided into three I/O ports, Port-A, Port-B, and Port-C. Besides I/O function, Port-B/C can also be used as LCD segment drives. For detail pin assignment, please refer to TABLE 10-1 PORT NAME PAD NAME PA0/INTX PA1 PA2 PA3 ...
Page 14
... IRT0 IRDAC IRX IET0 IEDAC IEX Bit 2 Bit 1 Bit 0 PCA[2] PCA[1] PCA[0] VCC DATA INPUT RD_INPUT FIGURE 10-1 Port-A Block Diagram Bit 2 Bit 1 Bit ST2032A Default 1111 1111 0000 0000 100 - - - - - - - 00 0000 - - 00 0000 Default 0000 0000 PULL-UP PMOS Default 100 - - -00 9/13/07 ...
Page 15
... Set input mode. #$FF < PULL-UP. <PA ; Keep last state. <IREQ ; Clear IRQ flag. <IENA ; Enable INT <PA ; Keep last state. DFF D Q XNOR2 OR2 CK DFF Q D XNOR2 CK OR2 DFF D Q XNOR2 CK OR2 DFF D Q XNOR2 CK OR2 PTIR High Level Interrupt NAND8 ST2032A 9/13/07 ...
Page 16
... Port-A Interrupt De-bounce ST2032A has hardware de-bounce block for Port-A interrupt enabled with “ 1” and disable with “ 0” of PDBN(PMCR[6]). The de-bounce function is activated by Port-A transition. It uses TABLE 10-5 Port Function Control Register (PMCR) Address Name R/W Bit 7 $00F PMCR R/W PULL ...
Page 17
... Bit 0 PCB[2] PCB[1] PCB[0] Bit 2 Bit 1 Bit 0 PCC[2] PCC[1] PCC[0] VCC PULL-UP PMOS DATA INPUT RD_INPUT Bit 2 Bit 1 Bit ST2032A Default 1111 1111 1111 1111 0000 0000 0000 0000 100 - - - - - - - - 1 1111 Default 0000 0000 Default 0000 0000 Default 100 - - - - - 9/13/07 ...
Page 18
... ST2032A has dual clock sources, OSC (RC) and OSCX (32768Hz crystal). The system clock (SYSCK) can be switched between OSC and OSCX, and is controlled by XSEL (SYS[7]). When system clock is switched, the warm-up cycles occur at the same time. Clock source being used is shown at ...
Page 19
... 12.1 Prescaler 12.1.1 Function Description The ST2032A has three timers, Base timer, Timer 0 and Timer 1, and two prescalers PRES and PREW. There are two clock Address Name R/W Bit 7 $021 BTM PRS[7] $023 PRS W SRES $024 T0M ...
Page 20
... PRES and Timer1 will get a 16bit-event counter. TABLE 12-2 Prescaler Control Register (PRS) Bit 6 Bit 5 Bit 4 Bit 3 PRS[6] PRS[5] PRS[4] PRS[3] SENA SENT - - timer1. It stops counting only if OSCX stops or hardware reset occurs. 20/54 Bit 2 Bit 1 Bit 0 Default PRS[2] PRS[1] PRS[0] 0000 0000 - - - 000 - - - - - ST2032A 9/13/07 ...
Page 21
... Bit - UP Counter IRBT CLOCK OUT Base Timer source clock STOP TCLK / 65536 TCLK / 32768 TCLK / 8192 TCLK / 2048 TCLK / 256 TCLK / 32 TCLK / 8 TCLK / 2 OSCX / 256 OSCX / 64 OSCX / 16 OSCX / 4 ST2032A 9/13/07 ...
Page 22
... Bit 3 Bit 2 Bit 1 Bit 0 T0C[3] T0C[2] T0C[1] T0C[0] ST2032A IRT0 Default 0000 0000 9/13/07 ...
Page 23
... TCLK stop 1 : TCLK counting 23/54 D Flip-Flop OUT D Q SYSCK CK 8 Bit - UP Counter CLOCK Auto Reload Bit 2 Bit 1 Bit 0 T1C[2] T1C[1] T1C[0] T1 Timer Clock Source TCLK/65536 TCLK/32768 TCLK/8192 TCLK/2048 TCLK/256 TCLK/32 TCLK/8 TCLK/2 OSCX/256 OSCX/128 OSCX/64 OSCX/32 ST2032A IRT1 Default 0000 0000 9/13/07 ...
Page 24
... PS: In order to make sure the PSG function is working normally on the EV or Real Chip Board, Please connect PSG‘ s power PVCC to VCC Ver 2.4 FIGURE 13-1. ST2032A has three playing modes. First is that both channel0 (CH0) and channel1 (CH1) output square type tones. Second is CH0 outputs square tone, and CH1 outputs noise ...
Page 25
... Hz) (PSGCK must >= 20K Hz) FIGURE 13-3 and.FIGURE 13-4. 12 Bit Auto-reload Up Counter C0[11~8] OUTPUT C0[7~0] Channel 0 Latch Enable CLOCK FIGURE 13-3 Tone Generator Channel 0 25/54 ST2032A Bit 2 Bit 1 Bit 0 Default PSG0[2] PSG0[1] PSG0[0] 0000 0000 - - - - 0000 PSG1[2] PSG1[1] PSG1[0] 0000 0000 - - - - 0000 C1EN C0EN DACE=0 - 000 0000 ...
Page 26
... FIGURE 13-4 Tone Generator Channel 1 function. Noise or tone function is selected by PRBS. TABLE 13-3 PSG Control Register (PSGC) Bit 6 Bit 5 Bit 4 Bit 3 PCK[2] PCK[1] PCK[0] PRBS PCK[2] PCK[1] PCK[0] DMD[1] DMD[0] 26/54 ST2032A Tone out Bit 2 Bit 1 Bit 0 Default C1EN C0EN DACE=0 - 000 0000 INH DACE=1 - 000 0000 9/13/07 ...
Page 27
... PSG1[5~0]. 16-Stage White Noise Generator NCK OUTPUT CLOCK FIGURE 13-5 Noise Generator PSGO and PSGOB. Positive part of the AC signal is output from PSGO while the negative part is from PSGOB. S T2032A FIGURE 13-6 PSG Application Circuit 27/54 OUTPUT Noise out Buzze r ST2032A 9/13/07 ...
Page 28
... DAC[1] DAC[ C1EN C0EN DACE DMD[0] INH DACE Bit 2 Bit 1 Bit 0 Default DAC[2] DAC[1] DAC[0] 0000 0000 Bit 2 Bit 1 Bit 0 Default C1EN C0EN DACE=0 - 000 00-0 DMD[0] INH DACE=1 - 000 0000 ST2032A 9/13/07 ...
Page 29
... Output Select FIGURE 14-2 DAC Clock Source Control PWM Frequency PSGC B6, B5, B4 32K 32K 29/54 BD BDB Reload_DAC PSGC PSGCK SYSCK SYSCK SYSCK SYSCK SYSCK 2MHz) OSC PSG1H, PSG1L 100 00001111, 00111111 100 00001111, 10111111 ST2032A 9/13/07 ...
Page 30
... DAC mode is controlled by DMD[1~0]. (TABLE 13-3) the time up to 100% high. As the value goes from 0 to -64, the duty cycle decreases from 50% high to 0%. PSGOB is inverse of PSGO’ s waveform. Figure 13-3 shows the PSGO waveforms DAC = 32 FIGURE 14-3 Single-Pin Mode Wave Form 30/54 32 64+X 96 64-X DAC = -32 DAC = X ST2032A 9/13/07 ...
Page 31
... PSGO goes high for X segments while PSGOB stays high. For a negative output value x=0 to -127, PSGOB goes low for |X| segments while PSGO stays low DAC = 32 DAC = DAC = -48 vdd ST2032A SPK 2.5K PSGOB 8050 PSGO 2.8K 31/54 96 127 32 DAC = 127 DAC = 0 DAC = -128 4.7uf ST2032A 1 9/13/07 ...
Page 32
... PSGO goes high for X segments while PSGOB stays low. For a negative output value x=0 to -127, PSGOB goes high for |X| segments while PSGO stays low DAC = 32 DAC = DAC = -48 DAC = 0 S T2032A 32/54 96 127 32 1 DAC = 127 DAC = -128 Buzze r ST2032A 9/13/07 ...
Page 33
... ST2032A is capable of driving one 1/16 duty, 1/5 bias LCD panel of segment number from 20 to 36(up to 576 dots). LCD block includes display frame buffer ($1000~ $10A3) for storing display data, 16 common and 20 segment dedicated drives. The rest 16 segment drives are shared with two I/O ports, Port-B/C. Data in frame buffer is undefined after power on, so correct frame data should be filled in before turn on display ...
Page 34
... PC4 PC5 PC6 PC7 PB0 PB1 PC5 PC6 PC7 PB0 PB1 PC6 PC7 PB0 PB1 PC7 PB0 PB1 PB0 PB1 PB1 34/54 ST2032A Bit 2 Bit 1 Bit 0 Default - - -1 1111 PAD PAD PAD PAD PAD PAD PB2 PB3 PB4 PB5 PB6 ...
Page 35
... Bit 2 Bit 1 Bit 0 Default CTR[2] CTR[1] CTR[0] 1000 0000 8 8 (maximum (minimum) ST2032A 9/13/07 ...
Page 36
... Level 1(mini.) Clock Source OSCX (32768Hz) OSCX (32768Hz) OSC (2MHz) OSC (2MHz) OSC (4MHz) OSC (4MHz) OSC (8MHz) OSC (8MHz) 36/54 Bit 2 Bit 1 Bit 0 Default LCK[2] LCK[1] LCK[0] 111- -000 : : 1/16 Duty consumption (uA) 69.28 65.64 61.96 58.31 54.63 50.95 47.27 43.6 39.91 36.22 32.52 28.82 25.1 21.4 17.66 13.82 Frame Rate ST2032A 9/13/07 ...
Page 37
... Interrupt Request Register . . CLI . . Ver 2.4 Note: 1. keyboard awaking pulses can only be turned on below 3V operating voltage there is crosstalk on the first line, please turn on keyboard-scan function for better quality. Initial I/O (Disable Debouncd) Initial Interrupt/LCD FIGURE 14-5 Initial Flow Chart 37/54 ST2032A CLI . . . 9/13/07 ...
Page 38
... LDA <ScanValue BCS ?Scan_PB ;;Keep on scanning until ScanValue = PLX PLA RTI Ver 2.4 Output Scan Value on Wait Port Stable No FIGURE 14-6 Port Interrupt Flow Chart 38/54 ST2032A Scan Lines Turn ON Port-B Read Port-A Turn OFF Port-B Store Key Data End of Scanning? Yes RTI 9/13/07 ...
Page 39
... Bit5 Bit5 … … Bit4 Bit4 Bit3 Bit3 Bit2 Bit2 … … Bit1 Bit1 Bit0 Bit0 1085H 10A3H Bit7 Bit7 … … Bit6 Bit6 Bit5 Bit5 … … Bit4 Bit4 Bit3 Bit3 Bit2 Bit2 … … Bit1 Bit1 Bit0 Bit0 ST2032A 9/13/07 ...
Page 40
... ST2032A has three power down modes: WAI-0, WAI-1 and STP. The instruction WAI will enable either WAI-0 or WAI-1, which is controlled by WAIT(SYS[2]). And the instruction Address Name R/W Bit 7 $030 SYS R/W XSEL Bit 3: WSKP : System warm-up control bit ...
Page 41
... Base OSC OSCX RAM REG. Timer Retain Stop Retain Stop Retain Base OSC OSCX RAM REG. Timer Retain Retain Retain 41/54 LCD I/O Wake-up condition Reset, Any interrupt Reset, Any interrupt Reset LCD I/O Wake-up condition Reset, Any interrupt Reset, Any interrupt Reset ST2032A 9/13/07 ...
Page 42
... ST2032A has a built-in low voltage detector for power management. When LVDET is set, detector circuit is enabled and the detection result will be outputted at the same bit after 3 ms. Using read instruction twice can get this result: first read will enable initial stableness control. ...
Page 43
... LCD Clock source=OSCX Driving strength=16/16 Condition: WAIT1 mode. PORT A, PORT B, PORT C RESET , INT PORT A, PORT B, PORT C RESET , INT PORTA (Voltage difference=0.9V). Operation voltage=5V PORTA (IOH=-3.5mA) PORTB, PORTC (IOH=-2.5mA) PORTA (IOL=7.5mA) PORTB, PORT C (IOL=4.5mA) PSG/DAC, IOH = -25mA. PSG/DAC, IOL= 53mA. ST2032A 9/13/07 ...
Page 44
... FIGURE 18-1 Relation between operation voltage & frequency 5000 4000 3000 2000 1000 2 Voltage Freq. 4MHz 2MHz Ver 2.4 Fosc 2.5 3 Voltage(V) TABLE 18-1 R-Oscillator V.S. Frequency 3V 47Kohm 100Kohm 44/54 ST2032A R=43.6K R=104K 3.5 4 9/13/07 ...
Page 45
... VDD : 3V Clock : 32768Hz crystal and 2.0MHz RC oscillator LCD : 1/16 duty I/O : PORT-A ALARM : PSGO, PSGOB FIGURE 19-1 Application Circuit without LCD keyboard awaking pulse Ver 2 45/54 ST2032A 9/13/07 ...
Page 46
... FIGURE 19-2 Application Circuit with LCD keyboard awaking pulse Ver 2.4 Note: Because the COMs and SEGs output VDD level while the LCD is turned off. There is no keyboard awaking pulse to wake up the system. So the ON/OFF key must connect between GND and Port-A. 46/54 ST2032A 9/13/07 ...
Page 47
... VDD : 5V Clock : 32768Hz crystal and 2.0MHz RC oscillator LCD : 1/16 duty I/O : PORT-A/B/C ALARM : PSGO, PSGOB FIGURE 19-3 Application circuit without DC-DC converter Ver 2.4 Note: LCD keyboard awaking pulses should be turned off under 5V operating voltage. 47/54 ST2032A 9/13/07 ...
Page 48
... ST2032A EVB PCB113-1 FIGURE 19-4 The PCB 113-1 of ST2032A EVB Ver 2.4 48/54 ST2032A 9/13/07 ...
Page 49
... LCD Driving : LEVEL _______(1~16) LCD Frame Rate : 64Hz LCD panel Voltage(VOP)： LCD Keyboard Awaking Pulses： Low Voltage Detector： ST2032A EVB PCB Program file： ﹒ bin E.V. Board bios version： Check sum（ See appendix） ： Appendix： ...
Page 50
... Use LCD-EVchip to check LCD display quality. If there is crosstalk 25 on the first line, please turn on keyboard-scan function for better quality. Always disable interrupt function(by an “ SEI ” instruction) when 26 modify the IENAL,IENAH,IREQL and IREQH register 27 After Power on ,enter wait 0 mode 0.5s before normal operation Ver 2.4 Check 50/54 ST2032A / / Note 9/13/07 ...
Page 51
... According to your setting of contrast level， mapping to LCD panel’s parameter﹒ [ST2032] – 16（ frame rate = 64 Hz.） Contrast Level 1(light 12(dark) Ver 2.4 Manager ____________________ Equivalent Duty CTR[3:0] 1111 48.8 1110 41.0 1101 35.3 1100 31.0 1011 27.7 1010 25.0 1001 22.8 1000 20.9 0111 19.3 0110 18.0 0101 16.8 0100 16.0 51/54 ST2032A Check Note Bias 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 9/13/07 ...
Page 52
... Hz.） Contrast Level 1(light 8(dark) IC Power On Default. Ver 2.4 Equivalent Duty CTR[3:0] 1111 36.6 1110 30.7 1101 26.5 1100 23.3 1011 20.8 1010 18.7 1001 17.1 1000 16.0 52/54 ST2032A Bias 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 9/13/07 ...
Page 53
... PRS[7~0] : The low byte value of PRES counter Page48 Add ST2032A EVB photo Page49 Add checklist for customer to confirm ST2032A EVB PCB number… … … … … … … … … … .… .2007/5/21 Version2.2 Page10,18,19,40,42 Change register SYS bit4 XBAK to Test bit and must be set “ 0” ...
Page 54
... Sitronix products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where products failure could result in injury, or loss of life, or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. Ver 2.4 ;;Port-B/C Shared With SEGs 54/54 ST2032A 9/13/07 ...