st20-gp6 STMicroelectronics, st20-gp6 Datasheet - Page 66

• Manufacturer Part Number: st20-gp6
• Description: Gps Processor
• Manufacturer: STMicroelectronics

ST20-GP6
11 Low power controller
11.1 Low power control
The ST20-GP6 is designed for 0.35 micron, 3.3V CMOS technology and runs at speeds of up to
50 MHz. 3.3V operation provides reduced power consumption internally and allows the use of low
power peripherals. In addition, to further enhance the potential for battery operation, a low power
power-down mode is available.
The different power levels of the ST20-GP6 are listed below.
11.1.1 Power-down mode
Power-down mode can be achieved in one of two ways, as listed below.
The low power timer and alarm are provided to control the duration for which the global clock gen-
eration is stopped during low power mode. The timer and alarm registers can be set by the device
store instructions and read by the device load instructions.
The ST20-GP6 enters power-down when:
The ST20-GP6 exits power-down when:
In power-down mode the processor and all peripherals are stopped, including the external memory
controller and optionally the PLL. Effectively the internal clock is stopped and functional operation
is stalled. On restart the clock is restarted and the chip resumes normal functional operation.
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Operating power — power consumed during functional operation.
Stand-by power — power consumed during little or no activity. The CPU is idle but ready to
immediately respond to an interrupt/reschedule.
Power-down — internal clocks are stopped and power consumption is significantly reduced.
Functional operation is stalled. Normal functional operation can be resumed from previous
state as soon as the clocks are stable. All internal logic is static so no information is lost
during power down.
Power to most of the chip removed — only the real time clock supply (RTCVDD) power on.
Availability of direct clock input — this allows external control of clocking directly and thus
direct control of power consumption.
Internal global system clock may be stopped — in this case the external clock remains run-
ning. This mechanism allows the PLL to be kept running (if desired) so that wake up from
low power mode will be fast.
the low power alarm is programmed and started, via configuration registers, providing there
are no interrupts pending.
there is specific external pin activity (Interrupt pin);
the low power alarm counter reaches zero.