st20-gp6 STMicroelectronics, st20-gp6 Datasheet - Page 8
st20-gp6
Manufacturer Part Number
st20-gp6
Description
Gps Processor
Manufacturer
STMicroelectronics
Datasheet
1.ST20-GP6.pdf
(123 pages)
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ST20-GP6
Memory subsystem
The ST20-GP6 on-chip memory system provides 60 Mbytes/s internal data bandwidth, supporting
pipelined 2-cycle internal memory access at 30 ns cycle times. The ST20-GP6 memory system
consists of SRAM, ROM and a programmable external memory interface (EMI).
8/123
Interrupts
128K
ROM
12 channel GPS
Programmable
hardware DSP
Real time
controller
controller
interface
Interrupt
memory
power
clock
radio
GPS
Low
Figure 2.1 ST20-GP6 architectural block diagram
SRAM
64K
communications
input/output
Test access
control unit
Diagnostic
services
2 UART
System
Parallel
Serial
ST20
CPU
port
ST20-GP6
.
.
.
16
Reset
Clock
User position
output in
ASCII
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