IDT74LVC16374APFG8 IDT, Integrated Device Technology Inc, IDT74LVC16374APFG8 Datasheet

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IDT74LVC16374APFG8

Manufacturer Part Number
IDT74LVC16374APFG8
Description
IC FLIP FLOP 16BIT D 3ST 48TVSOP
Manufacturer
IDT, Integrated Device Technology Inc
Series
74LVCr
Type
D-Typer
Datasheet

Specifications of IDT74LVC16374APFG8

Function
Standard
Output Type
Tri-State Non Inverted
Number Of Elements
2
Number Of Bits Per Element
8
Frequency - Clock
150MHz
Delay Time - Propagation
4.5ns
Trigger Type
Positive Edge
Current - Output High, Low
24mA, 24mA
Voltage - Supply
2.3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-TVSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
74LVC16374APFG8
FEATURES:
• Typical t
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
• V
• V
• CMOS power levels (0.4μ μ μ μ μ W typ. static)
• All inputs, outputs, and I/O are 5V tolerant
• Supports hot insertion
• Available in SSOP, TSSOP, and TVSOP packages
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Reduced system switching noise
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
FUNCTIONAL BLOCK DIAGRAM
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
© 2006 Integrated Device Technology, Inc.
IDT74LVC16374A
3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
1
1
CLK
machine model (C = 200pF, R = 0)
1
OE
CC
CC
D
1
= 3.3V ± 0.3V, Normal Range
= 2.7V to 3.6V, Extended Range
INDUSTRIAL TEMPERATURE RANGE
1
48
47
SK(o)
(Output Skew) < 250ps
TO SEVEN OTHER CHANNELS
D
C
3.3V CMOS 16-BIT
EDGE-TRIGGERED D-TYPE
FLIP-FLOP WITH 3-STATE OUTPUTS,
5 VOLT TOLERANT I/O
2
1
Q
1
1
DESCRIPTION:
advanced dual metal CMOS technology. This high-speed, low-power
register is ideal for use as a buffer register for data synchronization and
storage. The Output Enable (OE) and clock (CLK) controls are organized
to operate this device as two 8-bit registers or one 16-bit register with
common clock. Flow-through organization of signal pins simplifies layout.
All inputs are designed with hysteresis for improved noise margin.
This feature allows the use of this device as a translator in a mixed 3.3V/
5V supply system.
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
2
2
CLK
2
OE
The LVC16374A 16-bit edge-triggered D-type flip-flop is built using
All pins of the LVC16374A can be driven from either 3.3V or 5V devices.
The LVC16374A has been designed with a ±24mA output driver. This
D
1
36
25
24
TO SEVEN OTHER CHANNELS
INDUSTRIAL TEMPERATURE RANGE
D
C
IDT74LVC16374A
OCTOBER 2008
DSC-4752/5
13
2
Q
1

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IDT74LVC16374APFG8 Summary of contents

Page 1

IDT74LVC16374A 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP FEATURES: • Typical t (Output Skew) < 250ps SK(o) • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF • 3.3V ± ...

Page 2

IDT74LVC16374A 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP PIN CONFIGURATION GND ...

Page 3

IDT74LVC16374A 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition –40°C to +85°C A Symbol Parameter V Input HIGH Voltage Level IH V Input LOW Voltage Level ...

Page 4

IDT74LVC16374A 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP OPERATING CHARACTERISTICS, V Symbol Parameter C Power Dissipation Capacitance per Flip-Flop Outputs enabled PD C Power Dissipation Capacitance per Flip-Flop Outputs disabled PD SWITCHING CHARACTERISTICS Symbol Parameter f MAX t Propagation Delay PLH ...

Page 5

IDT74LVC16374A 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS (1) (1) Symbol V = 3.3V±0. 2. LOAD V 2.7 2 1.5 1 300 300 LZ ...

Page 6

IDT74LVC16374A 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP ORDERING INFORMATION LVC Temp. Range Bus-Hold Family CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 XX XXXX Device Type Package PV PVG PA PAG PFG 374A 16 ...

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