74LVT16374ADGG,112 NXP Semiconductors, 74LVT16374ADGG,112 Datasheet - Page 2

IC 16BIT EDG-TRIG D FF 48TSSOP

74LVT16374ADGG,112

Manufacturer Part Number
74LVT16374ADGG,112
Description
IC 16BIT EDG-TRIG D FF 48TSSOP
Manufacturer
NXP Semiconductors
Series
74LVTr
Type
D-Type Busr

Specifications of 74LVT16374ADGG,112

Function
Standard
Output Type
Tri-State Non Inverted
Number Of Elements
2
Number Of Bits Per Element
8
Frequency - Clock
150MHz
Delay Time - Propagation
3ns
Trigger Type
Positive Edge
Current - Output High, Low
32mA, 64mA
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-TSSOP
Logic Family
LVT
Technology
BiCMOS
Number Of Bits
16
Number Of Elements
2
Clock-edge Trigger Type
Positive-Edge
Polarity
Non-Inverting
Operating Supply Voltage (typ)
3.3V
Propagation Delay Time
6ns
Low Level Output Current
64mA
High Level Output Current
-32mA
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935203010112
NXP Semiconductors
3. Ordering information
Table 1.
4. Functional diagram
74LVT_LVTH16374A_7
Product data sheet
Type number
74LVT16374ADL
74LVT16374ADGG
74LVTH16374ADGG
74LVT16374AEV
74LVTH16374ABQ
Fig 1.
48
25
24
Pin numbers are shown for SSOP48 and TSSOP48
packages only.
Logic symbol
1
Ordering information
1CP
1OE
2CP
2OE
1D0
1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7
2D0
2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7
47
36
13
2
1D1
2D1
46
35
14
3
Package
Temperature range Name
−40 °C to +85 °C
−40 °C to +85 °C
−40 °C to +85 °C
−40 °C to +85 °C
1D2
2D2
44
33
16
5
1D3
2D3
43
32
17
6
1D4
2D4
41
30
19
8
1D5
2D5
40
29
20
9
All information provided in this document is subject to legal disclaimers.
1D6
2D6
38
11
27
22
001aac369
SSOP48
TSSOP48
VFBGA56
HXQFN60U
1D7
2D7
37
12
26
23
Rev. 07 — 22 March 2010
74LVT16374A; 74LVTH16374A
Description
plastic shrink small outline package; 48 leads;
body width 7.5 mm
plastic thin shrink small outline package;
48 leads; body width 6.1 mm
plastic very thin fine-pitch ball grid array
package; 56 balls; body 4.5 × 7 × 0.65 mm
plastic thermal enhanced extremely thin quad
flat package; no leads; 60 terminals; UTLP
based; body 4 × 6 × 0.5 mm
Fig 2.
3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
Pin numbers are shown for SSOP48 and TSSOP48
packages only.
IEC logic symbol
2OE
1OE
1CP
2CP
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
48
24
25
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1
EN1
EN2
3D
4D
C3
C4
001aaa254
1
2
11
12
13
14
16
17
19
20
22
23
© NXP B.V. 2010. All rights reserved.
2
3
5
6
8
9
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
Version
SOT370-1
SOT362-1
SOT702-1
SOT1134-1
2 of 19

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