74LVT16374ADGG,112 NXP Semiconductors, 74LVT16374ADGG,112 Datasheet - Page 15

• Manufacturer Part Number: 74LVT16374ADGG,112
• Description: IC 16BIT EDG-TRIG D FF 48TSSOP
• Manufacturer: NXP Semiconductors
• Series: 74LVTr
• Type: D-Type Busr

Specifications of 74LVT16374ADGG,112

• Function: Standard
• Output Type: Tri-State Non Inverted
• Number Of Elements: 2
• Number Of Bits Per Element: 8
• Frequency - Clock: 150MHz
• Delay Time - Propagation: 3ns
• Trigger Type: Positive Edge
• Current - Output High, Low: 32mA, 64mA
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP
• Logic Family: LVT
• Technology: BiCMOS
• Number Of Bits: 16
• Number Of Elements: 2
• Clock-edge Trigger Type: Positive-Edge
• Polarity: Non-Inverting
• Operating Supply Voltage (typ): 3.3V
• Propagation Delay Time: 6ns
• Low Level Output Current: 64mA
• High Level Output Current: -32mA
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935203010112

NXP Semiconductors
Fig 14. Package outline SOT1134-1 (HXQFN60U)
74LVT_LVTH16374A_7
Product data sheet
HXQFN60U: plastic thermal enhanced extremely thin quad flat package; no leads;
60 terminals; UTLP based; body 4 x 6 x 0.5 mm
Dimensions
mm
SOT1134-1
Unit
Outline
version
max
nom
min
0.50
0.48
0.46
A
L
0.05
0.02
0.00
L
A
1
1
terminal 1
index area
w
e
v
0.35
0.30
0.25
R
terminal 1
index area
b
IEC
- - -
E
C
C
h
4.1
4.0
3.9
A
A10
D
A1
D2
D1
B
B7
B1
D6
D5
1.90
1.85
1.80
D
h
A11
A32
6.1
6.0
5.9
e
JEDEC
E
All information provided in this document is subject to legal disclaimers.
B20
- - -
B8
3.90
3.85
3.80
D
e
e
E
D
2
1
h
h
B10
B18
References
0
Rev. 07 — 22 March 2010
1/2 e
0.5
A16
A27
b
e
74LVT16374A; 74LVTH16374A
k
e
1
D7
D8
1
B11
B17
JEITA
- - -
D3
D4
A17
A26
B
scale
2.5
e
2.5
1/2 e
2
w
v
A
E
3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
e
e
3
e
3
C
C
3
A
4.5
e
e
4
B
4
5 mm
eR
0.5
A
0.25
0.20
0.15
A
k
1
0.35
0.30
0.25
y
1
L
C
detail X
European
projection
0.125
0.075
0.025
L
1
0.07
C
v
X
y
0.05
w
© NXP B.V. 2010. All rights reserved.
0.08
Issue date
y
08-12-17
09-01-22
sot1134-1_po
SOT1134-1
0.1
y
1
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