si3210 ETC-unknow, si3210 Datasheet - Page 35

• Manufacturer Part Number: si3210
• Description: Proslic Programmable Cmos Slic/codec With Ringing/battery Voltage Generation
• Manufacturer: ETC-unknow

In addition, the user must select the sinusoidal ringing
waveform by writing TSWS = 0 (direct Register 34,
bit 0).
Trapezoidal Ringing
In addition to the sinusoidal ringing waveform, the
ProSLIC
illustrates a trapezoidal ringing waveform with offset
V
To configure the ProSLIC for trapezoidal ringing, the
user should follow the same basic procedure as in the
Sinusoidal Ringing section, but using the following
equations:
RCO is a value which is added or subtracted from the
waveform to ramp the signal up or down in a linear
fashion. This value is a function of rise time, period, and
amplitude, where rise time and period are related
through the following equation for the crest factor of a
trapezoidal waveform.
where T = ringing period, and CF = desired crest factor.
For example, to generate a 71 V
signal, the equations are as follows:
ROFF
Figure 20. Trapezoidal Ringing Waveform
RNGY 20 Hz
.
V
TIP-RING
V
supports
ROFF
RNGX
RNGY
t
RCO
RI SE
=
1
-- -
2
=
t
RISE
trapezoidal
=
Desired V
-----------------------------------
--------------- - 8000
20 Hz
=
=
1
-- - Period 8000
2
3
-- - T 1
4
1
-------------------------------
t
R ISE
96 V
2 RNGX
T=1/freq


–
8000
---------- -
CF
PK
1
2
=
ringing.


PK
2
200
15
, 20 Hz ringing
=
time
C8h
Figure 20
Preliminary Rev. 1.11
For a crest factor of 1.3 and a period of 0.05 sec
(20 Hz), the rise time requirement is 0.0153 sec.
In addition, the user must select the trapezoidal ringing
waveform by writing TSWS = 1 in direct Register 34.
Ringing DC voltage Offset
A dc offset can be added to the ac ringing waveform by
defining
Register 19). The offset, V
signal when RVO is set to 1 (direct Register 34, bit 1).
The value of ROFF is calculated as follows:
Linefeed Considerations During Ringing
Care must be taken to keep the generated ringing signal
within the ringing voltage rails (GNDA and V
maintains proper biasing of the external bipolar
transistors. If the ringing signal nears the rails, a
distorted ringing signal and excessive power dissipation
in the external transistors will result.
To prevent this invalid operation, set the VBATH value
(direct Register 74) to a value higher than the maximum
peak ringing voltage. The discussion below outlines the
considerations and equations that govern the selection
of the VBATH setting for a particular desired peak
ringing voltage.
First, the required amount of ringing overhead voltage,
V
current through the load, I
gain of Q5 and Q6, and a reasonable voltage required
to keep Q5 and Q6 out of saturation. For ringing signals
up to V
However, to determine V
equations below.
where:
N
I
(max value = 2 mA), and
V
It is good practice to provide a buffer of a few more
milliamperes for I
OS
AC,PK
OVR
REN
is the offset current flowing in the line driver circuit
I
LOAD,PK
, is calculated based on the maximum value of
is the ringing REN load (max value = 5),
RNGX 71 V
Si3210/Si3211/Si3212
= amplitude of the ac ringing waveform.
PK
the
RCO 20 Hz , 1.3 crest factor
= 87 V, V
=
=
----------------------------------- -
0.0153 8000
V
------------------ -
offset
R
2 24235
AC ,PK
ROFF
LOAD
PK
LOAD,PK
=
OVR
+
71
----- - 2
96
voltage
OVR
=
I
OS
LOAD,PK
ROFF
V
----------------- - 2
to account for possible line
=
= 7.5 V is a safe value.
ROFF
96
=
for a specific case, use the
15
396
V
=
, is added to the ringing
AC,PK
=
24235
, the minimum current
in
018Ch
15
ROFF
----------------- -
6.9 k
N
=
R EN
5EABh
+
(indirect
I
OS
BAT
) to
35