si3210 ETC-unknow, si3210 Datasheet - Page 26

• Manufacturer Part Number: si3210
• Description: Proslic Programmable Cmos Slic/codec With Ringing/battery Voltage Generation
• Manufacturer: ETC-unknow

Si 3210/ Si3 211/S i32 12
Loop Closure Detection
A loop closure event signals that the terminal equipment
has gone off-hook during on-hook transmission or on-
hook active states. The ProSLIC performs loop closure
detection digitally using its on-chip monitor A/D
converter. The functional blocks required to implement
loop closure detection are shown in Figure 16. The
primary input to the system is the Loop Current Sense
value provided in the LCS register (direct Register 79).
The LCS value is processed in the Input Signal
Processor when the ProSLIC is in the on-hook
transmission or on-hook active linefeed state, as
indicated by the Linefeed Shadow register, LFS[2:0]
(direct Register 64). The data then feeds into a
programmable digital low-pass filter, which removes
unwanted ac signal components before threshold
detection.
The output of the low-pass filter is compared to a
programmable threshold, LCRT (indirect register 28).
The threshold comparator output feeds a programmable
debouncing filter. The output of the debouncing filter
remains in its present state unless the input remains in
the opposite state for the entire period of time
programmed by the loop closure debounce interval,
LCDI (direct Register 69). If the debounce interval has
been satisfied, the LCR bit will be set to indicate that a
valid loop closure has occurred. A loop closure interrupt
is generated if enabled by the LCIE bit (direct
Register 22). Table 24 lists the registers that must be
written or monitored to correctly detect a loop closure
condition.
Loop Closure Threshold Hysteresis
Silicon revisions C and higher support the addition of
programmable hysteresis to the loop closure threshold,
which can be enabled by setting HYSTEN = 1 (direct
Register 108, bit 0). The hysteresis is defined by LCRT
(indirect Register 28) and LCRTL (indirect Register 43),
26
LCS
LVS
Processor
LFS
Signal
Input
LCVE
ISP_OUT
Figure 16. Loop Closure Detection
HYSTEN
Digital
NCLR
LPF
Preliminary Rev. 1.11
Loop Closure
LCRT
Thres hold
LCRTL
–
+
Parameter
Loop Closure
Interrupt Pending
Loop Closure
Interrupt Enable
Loop Closure Threshold
Loop Closure
Threshold—Lower
Loop Closure Filter
Coefficient
Loop Closure Detect
Status (monitor only)
Loop Closure Detect
Debounce Interval
Hysteresis Enable
Voltage-Based Loop
Closure
which set the upper and lower bounds, respectively.
Voltage-Based Loop Closure Detection
Silicon revisions C and higher also support an optional
voltage-based loop closure detection mode, which is
enabled by setting LCVE = 1 (direct Register 108,
bit 2). In this mode the loop voltage is compared to the
loop closure threshold register (LCRT) which represents
a minimum voltage threshold instead of a maximum
current threshold. If hysteresis is also enabled, then
LCRT represents the upper voltage boundary and
LCRTL represents the lower voltage boundary for
hysteresis.
detection is an option, the default current-based loop
closure detection is recommended.
Linefeed Calibration
Table 24. Register Set for Loop
D ebounce
Filter
LCDI
Although
Closure Detection
LCR
voltage-based
NCLR[12:0] Indirect Reg. 35
LCRTL[5:0] Indirect Reg. 43
LCRT[5:0]
LCDI[6:0]
Register
HYSTEN
LCVE
Interrupt
LCIP
LCIE
LCR
Logic
LCIE
LCIP
Indirect Reg. 28
Direct Reg. 108
Direct Reg. 108
Direct Reg. 19
Direct Reg. 22
Direct Reg. 68
Direct Reg. 69
loop
Location
closure