si3210 ETC-unknow, si3210 Datasheet - Page 106

• Manufacturer Part Number: si3210
• Description: Proslic Programmable Cmos Slic/codec With Ringing/battery Voltage Generation
• Manufacturer: ETC-unknow

Si 3210/ Si3 211/S i32 12
Register 108. Enhancement Enable
Note: The Enhancement Enable register and associated features are available in silicon revisions C and later.
Reset settings = 0000_0000
Reset settings = 0000_0000
106
Name
Name
Type
Type
Bit
7
6
5
Bit
Bit
ILIMEN
ILIMEN
ILIMEN
FSKEN
R/W
R/W
Name
DCSU
D7
D7
FSKEN
FSKEN
R/W
R/W
D6
D6
Current Limit Increase.
When enabled, this bit temporarily increases the maximum differential current limit at the
end of a ring burst to enable a faster settling time to a dc linefeed state.
0 = The value programmed in ILIM (direct Register 71) is used.
1 = The maximum differential loop current limit is temporarily increased to 41 mA.
FSK Generation Enhancement.
When enabled, this bit will increase the clocking rate of tone generator 1 to 24 kHz only
when the REL bit (direct Register 32, bit 6) is set. Also, dedicated oscillator registers are
used for FSK generation (indirect registers 99–104). Audio tones are generated using
this new higher frequency, and oscillator 1 active and inactive timers have a finer bit res-
olution of 41.67 s. This provides greater resolution during FSK caller ID signal genera-
tion.
0 = Tone generator always clocked at 8 kHz; OSC1, OSC1X., and OSC1Y are always
used.
1 = Tone generator module clocked at 24 kHz and dedicated FSK registers used only
when REL = 1; otherwise clocked at 8 kHz.
DC-DC Converter Control Speedup (Si3210 only).
When enabled, this bit invokes a multi-threshold error control algorithm which allows the
dc-dc converter to adjust more quickly to voltage changes.
0 = Normal control algorithm used.
1 = Multi-threshold error control algorithm used.
DCSU
R/W
D5
D5
Si3211/Si3212
ZSEXT
ZSEXT
Preliminary Rev. 1.11
R/W
R/W
Si3210
D4
D4
SWDB
R/W
D3
D3
Function
LCVE
LCVE
R/W
R/W
D2
D2
DCFIL
R/W
D1
D1
HYSTEN
HYSTEN
R/W
R/W
D0
D0